AT89C5132
Bit
Bit
Number
Mnemonic Description
Reserved
The values read from these Bits are always 0. Do not set these Bits.
7 - 4
-
Endpoint 3 Interrupt Enable Bit
EP3INTE Set to enable the interrupts for endpoint 3.
Clear to disable the interrupts for endpoint 3.
3
Endpoint 2 Interrupt Enable Bit
EP2INTE Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
2
1
0
Endpoint 1 Interrupt Enable Bit
EP1INTE Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
Endpoint 0 Interrupt Enable Bit
EP0INTE Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.
Reset Value = 0000 0000b
Table 66. UEPDATX Register
UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
Bit
Bit
Number
Mnemonic Description
Endpoint X FIFO Data
FDAT7:0 Data byte to be written to FIFO or data byte to be read from the FIFO, for the
Endpoint X (see EPNUM).
7 - 0
Reset Value = XXh
Table 67. UBYCTLX Register
UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)
7
-
6
5
4
3
2
1
0
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
Bit
Number
Bit
Mnemonic Description
Reserved
7
-
The values read from this Bits are always 0. Do not set this bit.
Byte Count
BYCT7:0 Byte count of a received data packet. This byte count is equal to the number of
data Bytes received after the Data PID.
6-0
Reset Value = 0000 0000b
79
4173E–USB–09/07
ATMEL [ ATMEL ]
