Figure 15-7. USB Interrupt Control Block Diagram
Endpoint x (x = 0.3)
TXCMP
UEPSTAX.0
RXOUT
UEPSTAX.1
EPxINT
UEPINT.x
RXSETUP
UEPSTAX.2
EPxIE
UEPIEN.x
STLCRC
UEPSTAX.3
USB interrupt
WUPCPU
USBINT.5
EUSB
IEN1.6
EWUPCPU
USBIEN.5
EORINT
USBINT.4
EEORINT
USBIEN.4
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0
ESPINT
USBIEN.0
15.3 Registers
Table 56. USBCON Register
USBCON (S:BCh) – USB Global Control Register
7
6
5
4
-
3
2
1
0
USBE
SUSPCLK SDRMWUP
UPRSM
RMWUPE
CONFG
FADDEN
72
AT89C5132
4173E–USB–09/07