AT89C5132
Bit
Bit Number Mnemonic Description
USB Enable Bit
Set to enable the USB controller.
Clear to disable and reset the USB controller.
7
6
USBE
Suspend USB Clock Bit
SUSPCLK Set to disable the 48 MHz clock input (Resume Detection is still active).
Clear to enable the 48 MHz clock input.
Send Remote Wake-up Bit
Set to force an external interrupt on the USB controller for Remote Wake UP
purpose.
SDRMWUP An upstream resume is send only if the bit RMWUPE is set, all USB clocks are
enabled AND the USB bus was in SUSPEND state for at least 5 ms. See
5
UPRSM below.
Cleared by software.
Reserved
The values read from this bit is always 0. Do not set this bit.
4
3
-
Upstream Resume Bit (read only)
UPRSM
Set by hardware when SDRMWUP has been set and if RMWUPE is enabled.
Cleared by hardware after the upstream resume has been sent.
Remote Wake-up Enable Bit
Set to enable request an upstream resume signalling to the host.
Clear after the upstream resume has been indicated by RSMINPR.
2
RMWUPE
Note: Do not set this bit if the host has not set the
DEVICE_REMOTE_WAKEUP feature for the device.
Configuration Bit
Set after a SET_CONFIGURATION request with a non-zero value has been
correctly processed.
Cleared by software when a SET_CONFIGURATION request with a zero value
is received.
1
CONFG
Cleared by hardware on hardware reset or when an USB reset is detected on
the bus.
Function Address Enable Bit
Set by the device firmware after a successful status phase of a
SET_ADDRESS transaction. It shall not be cleared afterwards by the device
firmware.
0
FADDEN
Cleared by hardware on hardware reset or when an USB reset is received.
When this bit is cleared, the default function address is used (0).
Reset Value = 0000 0000b
Table 57. USBADDR Register
USBADDR (S:C6h) – USB Address Register
7
6
5
4
3
2
1
0
FEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
73
4173E–USB–09/07
ATMEL [ ATMEL ]
