AS3525-A/-B C22O22
Data Sheet, Confidential
0
c2_qs
r/w
quiescent state
0
Table 70 DBOP control register
Register
bits
Name
type
function
default
value
31:22
21
reserved
clr_pop_err
clr_push_err
W
Interrupt clear signal for
pop error interrupt
Interrupt clear signal for
push error interrupt
0
0
Writing 1 to this bit will clear the pop
error interrupt. Writing 0 has no effect.
Writing 1 to this bit will clear the push
error interrupt. Writing 0 has no effect
.
20
19
W
en_data
r/w
Tri-state enable for dout
bus
0
When set, dout bus is tri-stated when
there is no active write on the bus.
18
17
16
sdc
res_even
enw
r/w
r/w
r/w
short count bit
reset to even cycle
enable write
0
0
0
when set, next output cycle is even
0: write disabled
1: write enabled
15
14:13
strd
osm
r/w
r/w
start read
output serial mode
0
0
0: single word out
1: 2 serial words out
2: 4 serial words out
0: 8 bit data width
1: 16 bit data width
0: all IR disabled
1: IR enabled
12
11
ow
r/w
r/w
output data width
IR enable
0
ir_enable
10
9
8
ir_po_err
ir_pu_err
ir_e_en
r/w
r/w
r/w
IR enable on pop error
IR enable on push error
IR enable set on push
empty
0
0
0
7
6
ir_ae_en
ir_af_en
r/w
r/w
IR enable set on push
almost empty
IR enabbe set on push
almost full
IR enable set on push full
read strobe time
0
0
0
5
4:0
ir_f_en
rs_t
r/w
r/w
0x1F
Notes:
-
If the start read bit is issued by setting the strd bit to 1, a single read cycle is generated. After this read cycle the strd
bit is set to 0 again by HW.
-
-
If write is enabled by setting enw=1, no read is possible (strd does not cause any action).
res_even is a reset bit that defines the start of even/odd generated signals. With res_even bit set, the next output
cycle is a even cycle. Within this first even output cycle the res_even bit is set to 0 by the SW.
sdc selects the counter length for the timing generator. Default is end value of 31. With sdc set to 1, the count end
value is 15.
-
-
en_data is used as a tri-state enable for the dout bus . When set as 1, dout is tri-stated if there is no active write on
the bus . When this bit is set as 0, dout is bus is tri-stated only during the read cycle.
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