AS3525-A/-B C22O22
Data Sheet, Confidential
Timing Parameters
Also the time points for change from p0-p1 (t1) and p1-p2 (t2) can be programmed. For these programmable timing parameters each data output
cycle is divided into 32 steps. Both T1 and T2 can be in the range of 0 to 31. For short count bit set (sdc bit in control register), T1 and T2 must be
in the range of 0 to 15.
Figure 35 DBOP timing parameters
dout
D0
Tperiod
0
10
20
30
P0, P1, P2 = 0,1,0; T1=6, T2=10
P0, P1, P2 = 1,0,1; T1=14, T2=28
P0, P1, P2 = 0,0,1; T1<21, T2=21
dinStrobe; TS = 24
Even/odd generated signals
In addition to these timing parameters, signals can also be programmed to go active only during the even (0, 2, 4, …) or the odd cycles (1, 3, 5, …).
For example the indication of even/odd bytes for the case that two bytes in serial are transmitted can be used.
Two control bits are used to set this signal behaviour:
evenEnable, oddEnable. For default, both are set to 1 and both cycles will appear. For cases where even or odd should be omitted, set according
evenEnable/oddEnable to 0. With both set to 0, no cycles will appear at the output!
Following example illustrates a typical waveform for an output interface where the evenEnable=0 and oddEnable=1 for control signal C2. In this
example, C2 is an active high indication of the high byte (D1, D3, D5, …).
Figure 36 DBOP even/odd generated signals waveforms
quiescent state
quiescent state
even
odd
even
odd
even
odd
dout
xx
D0
D1
D2
D3
D4
D5
C0 = write
C1 = enable
C2 = high byte
C3 = chip select
Normally the even/odd cycles are toggling all the time, also if there are quiescent states in between. To have the possibility of defining a new start,
reset of this even/odd counter can be done via the res_even bit inside of the control register. With res_even set, the counter starts with an even
cycle. Res_even is then set to 0 again by SW at the new start.
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