AS3525-A/-B C22O22
Data Sheet, Confidential
Table 65 NAF interrupt clear register
Name
Base
Default
0x0018
NAFClear
AS3525_NAND_FLASH_BASE
Clear Register
Offset 0x0024
The NAFClear register clears interrupt status information and re-enables interrupt
detection.
Bit
Bit Name
Default Access
Bit Description
Reset of ‘FIFO error indication’ status bit
0: no action
6
clear6
-
-
-
-
W
W
W
W
1: bit 6 of NAFStatus is reset and interrupt 6 detection is
enabled
Reset of ‘FIFO full indication’ status bit
0: no action
1: bit 5 of NAFStatus is reset and interrupt 5 detection is
enabled
Reset of ‘FIFO high indication’ status bit
0: no action
1: bit 4 of NAFStatus is reset and interrupt 4 detection is
enabled
Reset of ‘FIFO low indication’ status bit
0:no action
5
4
3
clear5
clear4
clear3
1:bit 3 of NAFStatus is reset and interrupt 3 detection is
enabled
Reset of ‘NAFWords empty and Controller ready indication’
status bit
2
clear2
-
W
0:no action
1:bit 2 of NAFStatus is reset and interrupt 2 detection is
enabled
Reset of ‘Read/write strobe ready indication’ status bit
0: no action
1
0
clear1
clear0
-
-
W
W
1: bit 1 of NAFStatus is reset and interrupt 1 detection is
enabled
Reset of ‘Read/write strobe ready indication’ status bit
0:no action
1: bit 0 of NAFStatus is reset and interrupt 0 detection is
enabled
Table 66 NAF test register
Name
Base
Default
0x0000
NAFTest
AS3525_NAND_FLASH_BASE
Test Register
Offset 0x0028
The NAFTest register is used for functional tests of the FIFO.
Bit
Bit Name
datainvert
Default Access
Bit Description
0: default mode
1
W
1: disables FIFO access by the internal controller => FIFO is
accessed by APB interface only
0: default mode
1: data word both on FIFO input and output is inverted
0
fifotest
-
W
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