AS3525-A/-B C22O22
Data Sheet, Confidential
Dbop Integration Test Registers
The Dbop module is programmed to integration test mode using test control register. The integration test mode enables the user to access all the
input/output pins through the APB bus interface.
Name
DBOPITC
DBOPITIP1
Offset
0x18
0x1C
R/W
Reset Value
Description
R/W
R/W
R
0x00000000
0x00
0x0
DBOP integration test control register
DBOP integration test input register
DBOP integration test output register
DBOPITOP1
0x20
Table 72 DBOPITC test register
Register
bits
Name
type
function
default
value
31:1
reserved
0
iten
r/w
Integration test enable
1 will enable the integration test
mode
Table 73 DBOPITIP1 test register
Register
bits
Name
type
function
default
value
31:5
reserved
4
3
2
1
0
Testctrloen
Testdataoen
Testdmasreq
Testdmabreq
testirq
r/w
Test value for
out_enControl_n
Test value for
out_enData_n
Test value for DMASREQ
0
0
0
0
0
The value on this bit will be
reflected in out_enControl_n
The value on this bit will be
reflected in out_enData_n
The value on this bit will be
r/w
r/w
r/w
r/w
reflected in
DBOPDMACSREQ
Test value for DMABREQ
Test value for interrupt
The value on this bit will be
reflected in
DBOPDMACBREQ
The value on this bit will be
reflected in DBOPIRQ
Table 74 DBOPITOP1 test register
Register
bits
Name
type
function
default
value
31:1
reserved
0
Testdmaclr
r
DBOPDMACCLR test
register.
0
Read of this register will return the
value on the
DBOPDMACCLR input.
7.3.12.2 DBOP DMA Interface
This block generates all necessary interface signals with the DMAC primecell for DMA transfer. Following table gives a description of these signals.
DBOPDMASREQ
DBOPDMABREQ
DBOPDMACLR
single word request, asserted by DBOP. This signal is asserted when there is at least one
empty location in the FiFo
burst DMA transfer request, asserted by DBOP. This signal is asserted when there are at
least four empty locations in the FiFo
DMA request clear, asserted by DMA controller to clear the DMA request signals. If DMA
burst transfer is requested, the clear signal is asserted during the transfer of the last data
in the burst
Symmetric FiFo
The FiFo buffer has two main purposes:
•
data buffering: the FiFo contains 128 locations with 32 bits for data storage: with according DMA transfer, the data can be transferred in short
time without need for any SW control
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