AS3525-A/-B C22O22
Data Sheet, Confidential
Table 63 NAF FiFo Data register
Name
Base
AS3525_NAND_FLASH_BASE
Default
0x0000
NAFFifodata
FIFO Data Register
Offset 0x001c
The NAFFifodata register offers access to the internal FIFO.
Bit
Bit Name
Default Access
Bit Description
Writing this register will push a word on the FIFO and the write
address will be incremented by 1. When the FIFO is full (36
words) then a write access on the register is ignored and the
FIFO ERROR status bit is set.
Reading on this register will pop a word from the FIFO and the
read address will be incremented by 1. When the FIFO is
empty then a read access on the register is ignored and the
FIFO ERROR status bit is set.
32:0
Fifodata [32:0]
-
R/W
Table 64 NAF interrupt mask register
Name
Base
AS3525_NAND_FLASH_BASE
Interrupt Mask Register
Default
0x0000
NAFWords
Offset 0x0020
The NAFWords register informs the controller about the maximum words to be
transferred and controls the FIFO transfer both in interrupt and DMA mode.
Bit
32:0
Bit Name
Default Access
Bit Description
0: FIFO based data transfer is disabled
not 0: FIFO transfer is in progress
Words [32:0]
0x0000 R/W
Note: For page transfers (program or read) the initial number of words depends on the NAND flash device. For a page size of 512 bytes, an initial
word value of 512/4 = 128 has to be written. For a page size of 2k bytes, an initial word value of 512 has to be used.
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