AS3525-A/-B C22O22
Data Sheet, Confidential
Table 71: DBOP status register
Register
bits
Name
type
function
default
value
31:17
reserved
16
15:12
11
10
9
8
7
6
5
4
3
2
1
rd_d_valid
Reserved
fi_pu_err
fi_pu_e
fi_pu_ae
fi_pu_hf
fi_pu_af
fi_pu_f
fi_po_err
fi_po_e
fi_po_ae
fi_po_hf
fi_po_af
fi_po_f
r
read data valid
f
push error
r
r
r
r
r
r
r
r
r
r
r
push fifo empty
push fifo almost empty
push fifo half full
push fifo almost full
push fifo full
pop error
pop fifo empty
pop fifo almost empty
pop fifo half full
pop fifo almost full
pop fifo full
0
The read data valid flag is cleared with every start read and set after read data strobe is issued (at read data valid 1 the
data can be readout by SW).
Data Output Register
32 bit register for data output - the data written to this register are directly written to the FiFo. Depending on the serial
output mode and the output data width, the effective register width of this register is 8, 16 or 32 bits.
Following table shows the effective data width for this register:
osm=0
osm=1
osm=2
odw = 0
odw = 1
8 (byte0)
16 (HW0)
16 (byte0, byte1)
32 (HW0, HW1)
32 (byte0, byte1, byte2, byte3)
32 (HW0, HW1)
Depending on odw,
•
•
either one, two or four bytes are transmitted serially for odw=0
or one or two half words (HW = 16 bits) are transmitted serially for odw=1.
Note that for the 8 or 16 bit width only a part of the FiFo memory is used (to keep HW design simple).
Data Input Register
16 bit data input register that holds the value of the last read cycle. It is only valid if the data valid flag is set in the status
register. No interrupt support is given, for data input the read data valid flag must be polled.
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