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A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS3525-A/-B C22O22  
Data Sheet, Confidential  
7.3.12 DBOP - Data Block Output Port  
Purpose of this ARM APB peripheral module is a high-speed data output port that can support data transfer to various display controllers based on  
synchronous control interfaces. Programmability of polarity and timing of the generated control signals makes it possible to support various kinds of  
displays. Example of a supported display controller is the Hitachi HD77766R LCDE controller.  
From the programmers point of view the DBOP module can be serviced by DMA accesses. With the large size of the data FIFO and the  
programmable interrupt request conditions the overhead for SW is minimised. Simple read instructions to read for example a status register of the  
LCD controller are also supported.  
The usage of this cell results in a great performance boost compared to the standard ARM GPIO PrimeCell™ architecture.  
Features  
APB bus interface  
support for direct memory access (DMA)  
data output FIFO with 128 words (32 bit wide)  
8 or 16 bit parallel data output (configurable)  
4 control outputs - flexible programming of the signal waveforms with respect to polarity and timing  
programmable even/odd control output generation  
8 or 16 bit parallel data input register with programmable read strobe  
programmable conditions for interrupt generation based on FIFO flags  
usage of FIFO for simple division of APB clock domain and output clock domain  
programmable data output rate in range of 0.05 to 4 MHz  
APB Clock & DBOP Clocks are synchronous.  
Figure 33 DBOP Block Diagram  
DBOP  
FiFo 128x32  
Dual ported  
RAM 128x32  
PRESETn  
PSEL  
32  
32  
Dout  
PENABLE  
dbop_d[7:0] / xpc[7:0]  
dbop_d[11:8] / xpb[7:4]  
register  
PWRITE  
Amba  
APB  
Interface  
push  
PADDR[11:2]  
pop  
lb_select,  
hb_select  
dbop_d[15:12]  
symetric FiFo  
Controller  
PWDATA[31:0]  
FiFo  
push  
status  
FiFo  
pop  
status  
PRDATA[7:0]  
PCLK  
c0 / xpb[0]  
c1 / xpb[1]  
Control  
Signal  
Generator  
c2 / xpb[2]  
c3 / xpb[3]  
Register  
Block  
dinStrobe  
dataValid  
8
Din register  
din[7:0]  
DBOPDMASREQ  
DBOPDMABREQ  
DMA  
Interface  
Interrupt  
Generator  
DBOPDMACLR  
DBOPIRQ  
dbop_clk  
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.  
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