AS3525-A/-B C22O22
Data Sheet, Confidential
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clock domain crossing: the FiFo is at the boarder of clock domain PCLK and DBOPCLK. All necessary synchronisation is done internally. All
flags are available as push flags (synchronised to the push clock PCLK) and pop flags (synchronised to the POP clk, which is synchronous to
DBOPCLK.
The FiFo controller gives empty, almost empty, half full, almost full and full flags which are available in two fashions: synchronous to the push or the
pop side (pop_empty, push_empty, …).
7.3.12.3 Control Signal Generator
Four independent control signals can be generated: typical application for such signals is a 80xx interface with RS, RD*, WR* and E or a 68xx
interface with RS, E, RWN. The idea of this control signal generator is a general-purpose block, which generates any signal timing/waveform that is
necessary to transfer the data to any specific display.
Polarity Parameters
For each of the control signals c0 - c3 following polarity parameters are defined:
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p0 … polarity 0 at start of cycle
p1 … polarity 1 following polarity 0
p2 … polarity 2 following polarity 1
Following figure shows an example for timing waveforms defined with these control parameters.
Figure 34 DBOP timing waveform
Tperiod
T1
T2
T1
T2
D1
D2
Static 0
NRZ 1
RZ 1
P0, P1, P2 = 000
P0, P1, P2 = 001
P0, P1, P2 = 010
P0, P1, P2 = 011
NRZ 1
RZ 1
P0, P1, P2 = 100
P0, P1, P2 = 101
RO 1
P0, P1, P2 = 110
P0, P1, P2 = 111
RZ 1
Static 1
Quiescent State
The control signals are only generated with each data output cycle (data output cycles are generated as long as the FiFo is not empty). With FiFo
empty and in the absence of a read cycle, all control signals are set to a quiescent state. For each control signal, this quiescent state can be
programmed either to 1 or 0.
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