AS3525-A/-B C22O22
Data Sheet, Confidential
Table 52 I2S output raw status register
Name
Base
Default
0x00
I2SOUT_RAW_STATUS
AS3525_I2SOUT_BASE
Raw status register
The read-only raw status register contains the actual bit values as reflected by the
FIFO controller status signals. I2SOUT_POER and I2SOUT_PUER are static bits,
since FIFO controller gives the PUSH/POP error bit only for one clock. This means
that these two bits remain asserted until they are cleared in the I2SOUT_CLEAR
register. All other bits change state depending on the underlying logic, i.e. state of
FIFO controller.
Offset: 0x0008
Bit
Bit Name
Default
Access
Bit Description
7
stereo18_status
0
R
Status of write interface for 18 bit stereo mode
0: left audio sample is expected next
1: right audio sample is expected next
1 if FIFO POP error
1 if FIFO PUSH is empty
1 if FIFO PUSH is almost empty
1 if FIFO PUSH is half full
1 if FIFO PUSH is almost full
1 if FIFO PUSH is full
1 if FIFO PUSH error
6
5
4
3
2
1
0
I2SOUT_POER
I2SOUT_PUE
I2SOUT_PUAE
I2SOUT_PUHF
I2SOUT_PUAF
I2SOUT_PUF
I2SOUT_PUER
0
0
0
0
0
0
0
R
R
R
R
R
R
R
Table 53 I2S output status register
Name
Base
Default
0x00
I2SOUT_STATUS
AS3525_I2SOUT_BASE
Status register
The status register is a read-only register. A read to this register returns the value
of the raw status bits AND’ed with the corresponding mask of enable bits set in the
mask register.
Offset: 0x000C
Bit
Bit Name
Default
Access
Bit Description
7
stereo18_status
0
R
Status of write interface for 18 bit stereo mode
0: left audio sample is expected next
1: right audio sample is expected next
1 if FIFO POP error
1 if FIFO PUSH is empty
1 if FIFO PUSH is almost empty
1 if FIFO PUSH is half full
1 if FIFO PUSH is almost full
1 if FIFO PUSH is full
1 if FIFO PUSH error
6
5
4
3
2
1
0
I2SOUT_POER
I2SOUT_PUE
I2SOUT_PUAE
I2SOUT_PUHF
I2SOUT_PUAF
I2SOUT_PUF
I2SOUT_PUER
0
0
0
0
0
0
0
R
R
R
R
R
R
R
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