AS3525-A/-B C22O22
Data Sheet, Confidential
Table 54 I2S output interrupt clear register
Name
Base
Default
0x00
I2SOUT_CLEAR
AS3525_I2SOUT_BASE
Interrupt clear register
The interrupt clear register is a write-only register. The corresponding static status
bit can be cleared by writing a 1 to the corresponding bit in the clear register. All
other interrupt flags are level interrupts depending on the status of the FIFO. The
bits are de-asserted depending on the FIFO controller.
Offset: 0x0010
Bit
Bit Name
Default
Access
Bit Description
Clear POP error interrupt flag
Clear PUSH error interrupt flag
7
6
5:1
0
reserved
I2SOUT_clear_poer
reserved
W
W
W
W
I2SOUT_clear_puer
I2SOUT_DATA
The I2SOUTIF provides two 32 bit wide data registers. The registers are used to store the audio samples before they are written to the FIFO. The
registers can be used in different modes depending on the setting of the I2SOUT_CONTROL register.
Basically, there are four ways to fill the FIFO.
The processor can provide
•
•
two 18 bit audio samples, one for each channel (R,L). The values are written to I2SOUT_DATA.
two 16 bit audio samples, one for each channel (R,L). Both values are written to the 32-bit wide I2SOUT_DATA register at
the same time. This mode is highly efficient for 32-bit processor architectures.
•
•
one 18 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SOUT_DATA.
one 16 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SOUT_DATA.
In 18 bit stereo mode the data in I2SOUT_DATA is interpreted either as left or right audio value. The stereo18_status bit in the I2SOUT_STATUS
register provides the information which channel’s audio sample is expected next.
The I2S Output Signals
The following specifications signals are given:
•
•
Data are valid at the rising edge of I2SO_SCLK.
The MSB is left justified to the I2S frame identification (I2SO_LRCK). According to standard I2S definition, a delay of one
clock cycle between transition of I2SO_LRCK and the data MSB is used.
The timing diagram of the I2S interface signals for 18bit and 16bit DAC is shown below.
Tperiod(fsaudio) / 2
Tperiod(fsaudio) / 2
I2SO_MCLK
I2SO_LRCK
Left Channel
Right Channel
I2SO_SCLK
I2SO_SDATA
15
17
2
1
0
2
15
17
2
1
0
2
16 bit
I2SO_SDATA
18 bit
1
0
1
0
Figure 29 - I2S output timing diagram
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