AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.9 SPDIF interface
As part of the I2SIN module also a SPDIF receiver interface is included. This SPDIF interface works as converter from SPDIF-AES/EBU to I2S.
The SPDIF-AES/EBU standard is a serial audio interface that conveys 2 time-multiplexed audio channels, the left and right channels, as is the case
in audio stereo transmission. The two channels are encoded in a 64-bit frame. Each individual channel is encoded in a sub-frame that consists of a
4-bit preamble, followed by 24 bits of audio data and 4 control bits, in a total of 32 bits per sub-frame. The SPDIF-AES/EBU standard provides for
LSB first, up to 24-bit audio samples, Samples of 20 bits or less may be used, in which case the 4 least significant bits may be used for a 12-bit
monitoring channel, transmitted at 1/3 of the sample rate. Please refer to the SPDIF-AES/EBU, AES3 or IEC958 standard documentation for more
information.
Features
•
Feed-forward operation: extracts audio data from the SPDIF-AES/EBU input signal by sampling it with a fast clock signal
which not necessarily related to the sample rate frequency
•
•
•
•
Purely digital receiver solution, without need of an input PLL for synchronisation.
The audio samples are output serially in I2S format.
PLL interface to filter out the jitter and generate a jitter-free I2S output.
Recognizes all common audio and video related sample frequencies and outputs a nibble code for each.
7.3.9.1 SPDIF register description
Table 48 SPDIF status register
Name
Base
Default
0x00
I2SIN_SPDIF_STATUS
AS3525_I2SIN_BASE
SPDIF status signals register
This read-only register contains status information of the SPDIF interface. The
spdif_sample_freq and spdif_sync status bits are directly derived from the SPDIF
converter. In order to provide valid status bits, these signals must be synchronized
with pclk, i.e. clk_i2sin.
Offset: 0x0018
Bit
Bit Name
Default
Access
Bit Description
Incoming sample frequency
Recognition of sub-frame preamble
4:1
0
spdif_sample_freq
spdif_sync
R
R
0: first sub-frame preamble not recognized
1: successful recognition of the first sub-frame preamble
The following table shows the input sample rate in KHz according to the sample_freq_code (bit 5 to 1) in the I2SIN_SPDIF register.
sample_freq_code Input Sample Rate (KHz)
22.050
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
24.000
32.000
44.100
48.000
64.000
88.200
96.000
176.400
192.000
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