AS3525-A/-B C22O22
Data Sheet, Confidential
Table 50 I2SOUT control register
Name
Base
Default
0x0C
I2SOUT_CONTROL
AS3525_I2SOUT_BASE
Control register
7 bit wide read/write register containing the control bits of the I2SOUTIF.
Offset: 0x0000
Bit
Bit Name
DMA_req_en
Default
Access
Bit Description
6
0
0
R/W
DMA request enable
0: disable
1: enable
5
sdata_lb
R/W
I2SDATA loopback from I2SINIF
0: I2SOUT_SDATA source is I2SOUTIF’s FIFO
1: I2SOUT_SDATA source is loopback value from I2SINIF
(signal I2SIN_FDATA)
4
mclk_invert
stereo_mode
18bit_mode
osr
0
1
1
R/W
R/W
R/W
R/W
Invert MCLK
0: disable (SCLK changes at MCLK’s falling edge)
1: enable (SCLK changes at MCLK’s rising edge)
Audio samples provided by processor
0: mono
3
1: stereo
2
Bit width of audio samples provided by processor
0: 16 bit
1: 18 bit
Oversampling rate
00: 128x
1,0
00
01: 256x
10: 512x
11: 128x
CAUTION: The control bit sdata_lb can only be set, if the I2SIN_FSDATA is synchronous to I2SOUT_SCLK. This is the case if AFE is used
together with the AS3525 (in this case the I2SINIF uses also I2SOUT_CLK).
Table 51 I2S Output mask register
Name
Base
Default
0x00
I2SOUT_MASK
AS3525_I2SOUT_BASE
Interrupt mask register
Offset: 0x0004
The interrupt mask register determines which status flags generate an interrupt by
setting the corresponding bit to 1.
Bit
Bit Name
reserved
Default
Access
Bit Description
7
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
stereo18_status cannot assert interrupt request
1 enables the FIFO POP error interrupt
6
5
4
3
2
1
0
I2SOUT_MASK_POER
I2SOUT_MASK_PUE
I2SOUT_MASK_PUAE
I2SOUT_MASK_PUHF
I2SOUT_MASK_PUAF
I2SOUT_MASK_PUF
I2SOUT_MASK_PUER
0
0
0
0
0
0
0
1 enables the FIFO PUSH is empty interrupt
1 enables the FIFO PUSH is almost empty interrupt
1 enables the FIFO PUSH is half full interrupt
1 enables the FIFO PUSH is almost full interrupt
1 enables the FIFO PUSH is full interrupt
1 enables the FIFO PUSH error interrupt
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