AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.10 I2SOUT - I2S output interface
The I2S output interface module (called I2SOUTIF module hereafter) is used to connect the processor system to an audio DAC. The
communication is based on the standardized I2S interface. The audio samples are transferred from the processor to the I2SOUTIF module using
the AMBA APB bus. A FIFO for 128 dual-channel audio samples is provided as a data buffer. Furthermore, the module provides a set of data,
control and status registers.
The I2SOUTIF provides the following features:
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•
•
•
•
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two independent clock domains: AMBA APB clock PCLK, I2S output clock i2so_mclk
FIFO (128 words with 36 bit) separating clock domains
support of 16 and 18 bit audio samples
clock generator for I2S clocks (LCLK, I2SO_SCLK)
support of several oversampling rates: 128x, 256x, 512x
interrupt support for FIFO data write
DMA support for FIFO data transfer
For data output, following modes are implemented:
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two 18 bit audio samples, one for each channel (R,L). The values are written to I2SO_DATA.
two 16 bit audio samples, one for each channel (R,L). Both values are written to the 32-bit wide I2SO_DATA register at the
same time. This mode is highly efficient for 32-bit processor architectures.
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one 18 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SO_DATA.
one 16 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SO_DATA.
Figure 28 I2SO Block Diagram
7.3.10.1 I2S Output Interface Registers
Table 49 I2S Output Interface Registers
Register Name
I2SOUT_CONTROL
I2SOUT_MASK
Base Address
AS3525_I2SOUT_BASE
AS3525_I2SOUT_BASE
AS3525_I2SOUT_BASE
AS3525_I2SOUT_BASE
AS3525_I2SOUT_BASE
AS3525_I2SOUT_BASE
Offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
Note
Control register
Interrupt mask register
Raw status register
Status register
I2SOUT_RAW_STATUS
I2SOUT_STATUS
I2SOUT_CLEAR
Interrupt clear register
Audio data register
I2SOUT_DATA
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