AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.8.5 DMA Interface
The I2SINIF supports DMA transfers. The DMA controller supports incrementing and non-incrementing (single address) addressing for source and
destination. For I2SINIF the single-address mode is used. The address of the I2SI_DATA register is used as DMA source address.
7.3.8.6 The 24 bit Stereo DMA Mode
In 24 bit stereo mode, right and left audio samples must be read separately from the FIFO. In single-address DMA-mode both data must be read
from the same address. The I2SINIF is responsible to split up the 48 bit FIFO entries into two 24 bit samples. The 24 bit value can then be
transferred via the 32 bit wide AMBA bus.
The I2SINIF provides the data in a specific order: first the left value is sent, and afterwards the right value is provided. Then a left value follows, and
so on. In the destination memory the words are stored incrementally as shown below.
Address
addr 0
Value
LDATA 0
RDATA 0
LDATA 1
RDATA 1
…
addr 1
addr 2
addr 3
…
addr n*2
addr n*2+1
LDATA n
RDATA n
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