AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.10.4 DMA Interface
The I2SOUTIF supports DMA transfers. The DMA controller supports incrementing and non-incrementing (single address) addressing for source
and destination. For I2SOUTIF the single-address mode is used. The address of the I2SOUT_DATA register is used as DMA destination address.
Stereo 18 bit DMA Mode
In 18 bit stereo mode, right and left audio samples must be transferred separately to the FIFO. In single-address DMA-mode both data must be
written to the same address. The I2SOUTIF is responsible to put the two 18 bit samples together to a 36 bit word. This word is written into the 36 bit
wide FIFO.
The I2SOUTIF requires a specific ordering of the samples written to the I2SOUT_DATA register: first the left value must be written, and afterwards
the DMA controller must write the right value. Then a left value can follow, a.s.o. The status bit stereo18_status shows which audio sample is
expected.
In order to set up a correct DMA transfer the values must be placed in the source memory as follows:
Address
Value
addr 0
addr 1
addr 2
addr 3
…
LDATA 0
RDATA 0
LDATA 1
RDATA 1
…
addr n*2
addr n*2+1
LDATA n
RDATA n
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