AS3525-A/-B C22O22
Data Sheet, Confidential
For the relationship of the clocks following constraints must be met:
•
LRCK must change with the falling edge of MCLK while MCLK is low (constrained should be set to 40 % of the MCLK period, see figure
below).
•
SDATA must change at the falling edge of SCLK. It will be read with the rising edge of SCLK.
Figure 30 Clock constraints
I2SO_MCLK
I2SO_LRCK
I2SO_SCLK
Lrck must change with falling edge,
within 40 % of MCLK period
Sampling of I2S data by Cello IF with rising edge of SCLK
L14 R15 R14
I2SO_SDATA
L15
7.3.10.2 Power Modes
The I2SOUTIF contains two clock domains. Each clock domain can be turned off separately. The I2SO_MCLK must be turned off in the global
clock controller register. This is necessary, as the audio chip requires I2SO_MCLK and I2SO_SCLK not only for I2S output, but also I2S input (see
I2SINIF).
PCLK Idle Mode
If the PCLK is turned off (by the clock controller) the I2SOUT_STATUS register can hold invalid data. However, no interrupt should be triggered if
the I2SOUTIF is in idle mode.
I2SO_MCLK Idle Mode
If I2SO_MCLK is disabled (by the clock controller) no audio samples are read from the FIFO. The output signals remain unchanged until the
I2SO_MCLK is enabled again.
7.3.10.3 Loopback Feature
On the AS3525 are two I2S interfaces:
•
•
I2SOUTIF is responsible to send values to the DAC of the audio chip via I2SO_SDATA
I2SINIF is responsible to receive audio values from ADC of the audio chip via I2SI_SDATA
In the AS3525 both SDATA signals are provided as loopback signals (I2SO_FSDATA, I2SI_FSDATA):
•
I2SO_SDATA to I2SINIF: This loopback is mainly for testing the transmission and reception paths of both I2S interfaces.
The loopback signal is called I2SO_FSDATA.
•
I2SI_SDATA to I2SOUTIF: This loopback feature allows the application to echo the input audio samples directly to a
loudspeaker. The signal provided by the I2SINIF is called I2SI_FSDATA.
In normal mode the I2SOUTIF generates the I2SO_SDATA signal based on the contents of the FIFO. If the loop back feature is enabled, the
SDATA_LB bit in the I2SOUT_CONTROL register must be set.
NOTE: This feature will only be available if SCLK is the same for I2S input and output interface. For implementation the I2SI_FSDATA signal is
simply routed through a multiplexer to the I2SO_SDATA interface.
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