AS3525-A/-B C22O22
Data Sheet, Confidential
Table 26 Peripheral Clock Controller Register
Name
Base
Default
CGU_PERI
AS3525_CGU_BASE
0x0F800000
Peripheral clock controller register
This register allows setting the peripheral clocks.
Default Bit Description
memory bist manager clock enable
Offset0x14
Bit
Bit Name
MBIST_EN
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EXTMEM_EN
EXTMEMIF_EN
1TRAM_EN
ROM_EN
external memory clock enable
external memory AHB IF clock enable
1TRAM controller AHB IF clock enable
ROM AHB IF clock enable
VIC_EN
vectored interrupt controller AHB IF clock enable
DMA controller AHB IF clock enable
USB controller AHB IF clock enable
I2Sout APB IF clock enable
DMAC_EN
USB_EN
I2SO_APB_EN
I2SI_APB_EN
I2C_EN
I2Sin APB IF clock enable
I2C master/slave APB IF clock enable
I2C audio APB IF clock enable
I2C_AUDIO_EN
GPIO_EN
general purpose IO APB IF clock enable
secure digital/multimedia APB IF clock enable
NAND flash/Smart Media APB IF clock enable
UART APB IF clock enable
SDMCI_EN
NANDFLASH_EN
UART_EN
WDOCNT_EN
WDOIF_EN
SSP_EN
watchdog counter clock enable
watchdog timer module APB IF clock enable
synchronous serial port APB IF clock enable
timer module timer1 clock enable
timer module timer2 clock enable
timer module APB IF clock enable
TIMER1_EN
TIMER2_EN
TIMERIF_EN
8
7
division ratio div1 (AHB/APB clock) => div1 = 1/(pclk_div1_sel
+ 1)
6
PCLK_DIV1_SEL
0
R/W
R/W
PCLK_DIV0_SEL
[3:0]
division ratio div0 (ext. memory clock) => div0
=
5:2
0x0
1/(pclk_div0_sel + 1)
clkin select
b’00: clk_main
b’01: plla_fout
b’10: pllb_fout
b’11: fclk
1:0
PCLK_SEL[1:0]
0x0
R/W
CAUTION: Clock gating takes effect immediately! Software must assure that all transactions to/from the module are finished
before the clock is disabled.
CAUTION: The peripheral clock must not exceed 65 MHz. The software must assure that requirement.
Note:
f(clk_extmem) := f(clkin) * div0;
f(pclk) := f(clkin) * div0 * div1;
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