AS3525-A/-B C22O22
Data Sheet, Confidential
Table 28 Processor USB Clock Controller Register
Name
Base
Default
0x00
CGU_USB
AS3525_CGU_BASE
USB Clock ControllerRegister
This register allows setting the USB PHY interface clock.
Offset0x1c
Bit
Bit Name
USB_CLK_EN
Default
Access
Bit Description
5
0x00
R/W
USB PHY clock enable => clk_usb
division ratio
4:2
USB_DIV_SEL [2:0]
USB_SEL[1:0]
0x00
0x00
R/W
R/W
0: div = 1/1
> 0: div = 1/(2*n); (even division factors only)
clkin select
00: clk_main
1:0
01: plla_fout
10: pllb_fout
11: reserved (clk_main)
Note:
The clock gating bit applies only to the USB PHY clock. To enable/disable the clock to the AHB part (USB CORE) CGU_PERI
has to be configured.
f(clk_usb) = f(clk_core_48m) = f(clkin) * div;
Table 29 Interrupt Mask and PLL Lock Status Register
Name
Base
Default
0x00
CGU_INTCTRL
AS3525_CGU_BASE
Interrupt Mask and PLL Lock Status Register
Offset: 0x20
Bit
Bit Name
Default
0x00
Access
Bit Description
3
INT_EN_PLLB_LOCK
R/W
interrupt on PLLB lock enable (R/W)
2
1
0
INT_EN_PLLA_LOCK
PLLB_LOCK
0x00
0x00
R/W
R
interrupt on PLLA lock enable (R/W)
PLLB lock status, locked if SET (not cleared on read)
PLLA lock status, locked if SET (not cleared on read)
PLLA_LOCK
R
Table 30 Interrupt Clear Register
Name
Base
Default
0x00
CGU_IRQ
AS3525_CGU_BASE
Interrupt Clear Register
Offset: 0x24
Bit
Bit Name
PLLB_LOCK
PLLA_LOCK
Default
Access
Bit Description
1
0
0x00
0x00
R
R
PLLB lock status, locked if SET (not cleared on read)
PLLA lock status, locked if SET (not cleared on read)
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com Revision 1.13
110 - 194
AMSCO [ AMS(艾迈斯) ]
