AS3525-A/-B C22O22
Data Sheet, Confidential
Table 23 PLLA Supervisor Register
Name
Base
Default
0x08
CGU_PLLASUP
AS3525_CGU_BASE
PLLA Supervisor Register
Offset0x08
This register contains control bits of the PLLA which are used very rarely, but have
major impact on the functionality of the system.
Bit
Bit Name
PLLA_PD
Default
0x00
Access
R/W
Bit Description
PLLA power down if SET
3
2
1
PLLA_OEB
PLLA_BP
0x00
R/W
PLLA output enable, active low
PLLA bypass if SET
0x00
R/W
PLLA clock source select
0: clk_int [PAD]
0
PLLA_FIN_SEL
0x00
R/W
1: clk_ext [PAD]
Table 24 PLBB Supervisor Register
Name
Base
Default
0x08
CGU_PLLBSUP
AS3525_CGU_BASE
PLLB Supervisor Register
Offset0x0c
This register contains control bits of the PLLB which are used very rarely, but have
major impact on the functionality of the system.
Bit
Bit Name
PLLB_PD
Default
0x00
Access
R/W
Bit Description
PLLB power down if SET
3
2
1
PLLB_OEB
PLLB_BP
0x00
R/W
PLLB output enable, active low
PLLB bypass if SET
0x00
R/W
PLLB clock source select
0: clk_int [PAD]
0
PLLB_FIN_SEL
0x00
R/W
1: clk_ext [PAD]
Table 25 Processor Clock Controller Register
Name
Base
Default
0x00
CGU_PROC
AS3525_CGU_BASE
Processor Clock Controller Register
This register contains control bits for ARM processor clock generation => FCLK.
Offset0x10
Bit
7:4
Bit Name
Default
Access
Bit Description
FCLK_POSTDIV_SEL
[3:0]
post divider division ratio => post_div =
1/(fclk_postdiv_sel + 1)
0x00
R/W
pre divider (fractional) division ratio
00: pre_div = 1/1
01: pre_div = 7/8
10: pre_div = 6/8
11: pre_div = 5/8
clkin select
FCLK_PREDIV_SEL
[1:0]
3:2
1:0
0x00
0x00
R/W
R/W
00: clk_main
01: plla_fout
FCLK_SEL[1:0]
10: pllb_fout
11: reserved (clk_main)
NOTE: f(fclk) := f(clkin) * pred_div * post_div;
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