AS3525-A/-B C22O22
Data Sheet, Confidential
Clock Constraining
Different clocks are constraint to different maximum clock speeds. As the clock frequencies can be set by software, care must be taken not to
exceed these maximum clock frequencies.
Table 879 Clock Constraining
Clock Domain
FCLK
Max. Freq. [MHz]
Description
250
65
90
65
30
48
90
40
Processor Clock
PCLK
AHB/APB bus clock
MPMC_CLK
I2SI MCLK
I2SO MCLK
USB CLK
IDE CLK
MPMC (external memory interface) clock
I2S input interface master clock
I2S output interface master clock
USB interface clock
IDE interface clock
MS CLK
Memory Stick Interface clock
Figure 42 Clock Generation Unit Block Diagram
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