AS3525-A/-B C22O22
Data Sheet, Confidential
Table 34 Memory Stick (MS) Clock Controller Register
Name
Base
Default
0x00
CGU_MS
AS3525_CGU_BASE
MS Clock Controller Register
This register allows setting the MS interface clocks.
Offset: 0x34
Bit
Bit Name
MSIF_CLK_EN
MS_CLK_EN
Default
Access
R/W
Bit Description
MS APB IF clock enable
8
7
0
0
R/W
MS IF clock enable (20/40MHz domain) => clk_ms
division ratio => div = 1/(ms_div_sel + 1)
6:2
MS_DIV_SEL [2:0]
0x0
R/W
clkin select (clk_ms)
00: clk_main
1:0
MS_SEL[1:0]
0x0
R/W
01: plla_fout
10: pllb_fout
11: reserved (clk_main)
Note: f(clk_ms) = f(clkin) * div;
Table 35 Data Block Output Port (DBOP) Clock Controller Register
Name
Base
AS3525_CGU_BASE
DBOP Clock Controller Register
This register allows setting the DBOP interface clocks.
Default
CGU_DBOP
0x00
Offset: 0x38
Bit
Bit Name
DBOP_EN
Default
Access
Bit Description
DBOP APB IF clock enable
3
0
R/W
DBOP_PREDIV_SEL
[2:0]
2:0
0x0
R/W
division ratio => div = 1/(dbop_prediv_sel + 1)
Note:
Setting DBOP_EN will enable both clocks (push/APB and pop) immediately.
clk_dbop clock (pop clock) generation uses DBOP APB IF clock as input clock.
f(clk_dbop) = f(PCLKDBOP) * div;
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