AS3525-A/-B C22O22
Data Sheet, Confidential
Table 27 Audio Clock Controller Register
Name
Base
Default
0x00
CGU_AUDIO
AS3525_CGU_BASE
Audio Clock Controller Register
This register allows setting the audio clock to I2S input and output interface.
Offset0x18
Bit
Bit Name
I2SI_MCLK2PAD_EN
I2SI_MCLK_EN
Default
Access
Bit Description
I2S audio input clock (I2SI_MCLK) to PAD connection
enable
24
23
0
R/W
0
R/W
R/W
I2S audio input clock (I2SI_MCLK) enable
I2SI_MCLK_DIV_SEL
[8:0]
I2Sin audio
IF clock division ratio => div_i
1/(i2si_mclk_div_sel + 1)
=
22:14
0x0
I2SI_MCLK clkin select
00: clk_main
13:12
ISI_MCLK_SEL[1:0]
0x0
R/W
01: plla_fout
10: pllb_fout
11: reserved (clk_main)
11
I2SO_MCLK_EN
0
R/W
R/W
I2S audio output clock (I2SO_MCLK) enable
I2SO_MCLK_DIV_SEL
[8:0]
I2Sout audio IF clock division ratio => div_o
1/(i2so_mclk_div_sel + 1)
=
10:2
0x0
I2SO_MCLK clkin select
00: clk_main
1:0
ISO_MCLK_SEL[1:0]
0x0
R/W
01: plla_fout
10: pllb_fout
11: reserved (clk_main)
Note:
The clock gating bits in this register apply only to the audio clocks. To enable/disable the APB parts of the corresponding I2S IF
CGU_PERI has to be configured.
f(i2si_mclk) := f(I2SI_mclk clkin) * div_i;
f(i2so_mclk) := f(I2SO_mclk clkin) * div_o;
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