AS3525-A/-B C22O22
Data Sheet, Confidential
Table 31 PLL A Lock Counter Register
Name
Base
Default
0x20
CGU_COUNTA
AS3525_CGU_BASE
PLL A Lock Counter Register
Offset: 0x28
Bit
7:0
Bit Name
COUNTA[7:0]
Default
0x00
Access
Bit Description
number of PLL A’s fout-clock cycles until the LOCKA
bit is set
R/W
Table 32 PLL B Lock Counter Register
Name
Base
Default
0x20
CGU_COUNTB
AS3525_CGU_BASE
PLL B Lock Counter Register
Offset: 0x2c
Bit
7:0
Bit Name
COUNTB[7:0]
Default
0x00
Access
Bit Description
number of PLL B’s fout-clock cycles until the LOCKB
bit is set
R/W
Table 33 IDE Clock Controller Register
Name
Base
Default
0x20
CGU_IDE
AS3525_CGU_BASE
IDE Clock Controller Register
This register allows setting the IDE interface clocks.
Offset: 0x30
Bit
Bit Name
IDEIF_CLK_EN
IDE_CLK_EN
Default
Access
R/W
Bit Description
IDE AHB IF clock enable
7
6
0
0
R/W
IDE IF clock enable (90MHz domain) => clk_ide
division ratio => div = 1/(ide_div_sel + 1)
5:2
IDE_DIV_SEL [2:0]
0x0
R/W
clkin select (clk_ide)
00: clk_main
1:0
IDE_SEL[1:0]
0x0
R/W
01: plla_fout
10: pllb_fout
11: reserved (clk_main)
Note: f(clk_ide) := f(clkin) * div;
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