AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.14.5 Clock Generation Unit Registers
Table 20 CGU Registers
Register Name
CGU_PLLA
Base Address
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
AS3525_CGU_BASE
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
Note
PLLA configuration register
CGU_PLLB
PLLB configuration register
PLLA supervisor register
CGU_PLLASUP
CGU_PLLBSUP
CGU_PROC
CGU_PERI
PLLB supervisor register
processor clock control register
peripheral clock control register
audio clock control register
USB clock control register
CGU_AUDIO
CGU_USB
CGU_INTCTRL
CGU_IRQ
CGU interrupt mask and enable register
interrupt clear and lock status register
PLLA lock counter register
CGU_COUNTA
CGU_COUNTB
CGU_IDE
PLLB lock counter register
IDE clock control register
CGU_MS
Memory Stick clock control register
DBOP clock controller register
CGU_DBOP
Table 21 CGU_PLLA Register
Name
Base
Default
0x00
CGU_PLLA
AS3525_CGU_BASE
PLLA Configuration Register
The CGU_PLLA register is used to configure the PLL A
Offset0x00
Bit
Bit Name
Default
Access
Bit Description
PLLA output divider control, 2 bit
14:13
PLLA_OD [1:0]
0x00
R/W
12:8
7:0
PLLA_R [4:0]
PLLA_F [7:0]
0x00
0x00
R/W
R/W
PLLA input divider control, 5-bit
PLLA feedback divider control, 8 bit
Table 22 CGU_PLLB Register
Name
Base
Default
0x00
CGU_PLLB
AS3525_CGU_BASE
PLLB Configuration Register
The CGU_PLLB register is used to configure the PLL B
Offset0x04
Bit
14:13
12:8
7:0
Bit Name
PLLB_OD [1:0]
PLLB_R [4:0]
PLLB_F [7:0]
Default
0x00
Access
R/W
Bit Description
PLLB output divider control, 2 bit
0x00
R/W
PLLB input divider control, 5-bit
0x00
R/W
PLLB feedback divider control, 8 bit
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