AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.14.4 PLL description
•
runs on single power supply at 1.2 V (special power PADs are used within the chip layout to guarantee lowest jitter:
vddapll, vssapll which are connected to vdd_core, vss_core within the BGA substrate)
fully integrated with internal loop filter
VCO operating frequency from 200 - 400 MHz
phase comparator input frequency from 2 - 8 MHz
•
•
•
•
low power dissipation of typical 2.5 mW
Figure 41 PLL block diagram
Programming and calculation of the PLL output frequency
The output frequency is controlled by three programmable dividers within the PLL. These dividers are: the input divider NR, the feedback divider NF
and the output divider NO. The divider settings are programmed by bits within CGU_PLLA, CGU_PLLB registers. The table on the following page
gives the detailed formulas for setting the PLL output frequency.
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.13
103 - 194
AMSCO [ AMS(艾迈斯) ]
