S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
The sequence of control signals and data presented to
the HIPPI channel by the Source device meet all the
requirements of the HIPPI specification. There is no
need for the Source Host to insert wait intervals
(dummy words) in the FIFO stream to provide the
required wait intervals between PACKET and BURST
(the FIFO can be 100% utilized for HIPPI
I-Field and data). The Source device will automatically
generate LLRC and append it to the end of each
terminated HIPPI Burst regardless of how the Burst
was terminated. It is the responsibility of the Source
Host to prevent multiple Short Bursts in one Packet.
input also latches the MODE_SELECT inputs on its
rising edge. The phase of the resulting 25 MHz clock
is controllable by the phase of the asserted RESET
mode described below.
SOURCE DEVICE OPERATING MODES
The Source device has several operating modes,
which require external selection by the Source Host.
Also provided is a ‘board test’ mode that may be used
by the Source Host as a part of a system diagnostic
routine. The Source Host selects the operating
mode with the two lines, MODE_SELECT_0 and
MODE_SELECT_1 [MSELx]. For numerical reference,
MODE_SELECT_1 is the most significant bit.
MODE_SELECT_2 should be held at a TTL logic zero
(ground) for in-board operation of the Source device.*
The Source device automatically formats the
transferred data into packets and bursts with LLRC.
The Source device counts the number of data words
received from the FIFO and uses this number as the
“seed” for the LLRC calculation.
Mode 0 (00 on mode select bus) is device reset. In
the reset mode, all internal registers are initialized,
and all device outputs are forced inactive including
the HIPPI Source-to-Destination INTERCONNECT
[SDIC] output. The ability to control the phase of the
25MHz clock (and the READ_CLOCK output) which
is generated by dividing the 50_MHZ input by 2 is
also provided by this mode.
DATA AND PARITY
The Source Host presents the HIPPI I-Field and
Data to the HIPPI Source device on the TTL DATA
AND PARITY interface.
32_DATA_+_4_PARITY (inputs) [DATxx,PARxx]
Mode 1 (01) is the board test mode. In this mode,
the Source device provides a means to verify
connection and operation of the interface between
the Source Host and the Source device completely
independent of the HIPPI channel. In this mode, the
Source-to-Destination INTERCONNECT [SDIC]
signal is forced inactive. When the Source Host
initiates a Connection Request by asserting
CONNECT_REQUEST, the Source device advances
the FIFO to the first I-Field, reads the I-Field, and then
simulates a Connect Accept on the HIPPI channel,
asserting the CONNECT_OUT and ACCEPT/ REJECT
signals to the Source Host. The Source Host will then
provide ‘test’ data bursts to the Source device
through the FIFO, as it would for a functional data
transfer, and the Source device will pass the ‘test’
data through the LLRC and parity check functions.
The data will also appear at the HIPPI-side data
outputs, but since the Source device is not in the
functional or wait Modes the Source-to-
Destination INTERCONNECT signal is inactive. The
only difference to the Source Host between a
functional transfer and a ‘test’ transfer is that the first
data word of each ‘test’ burst must be the expected
LLRC of the previous ‘test’ burst. By providing the
expected LLRC, the Source device can compare its
generated LLRC with the Host’s expected LLRC,
These lines are used for the I-Field during the connection
sequence and for data during Burst transfers.
INPUT_PARITY_ERROR (output) [INPRR]
Parity is checked just before the data leaves the
Source device (i.e. at the inputs to the differential
drivers of the HIPPI channel). Parity errors are
reported on a word by word basis. Upon detecting a
parity error for a given word, this signal is set high
for the duration of the next word’s clock cycle
(approximately 40 nsec).
Note: All parity errors are indicated but no recovery
action is taken by the Source device. If there is a
parity error detected, then the data and the bad
parity are passed through the Source.
CHIP STATUS/CONTROL
Overall control of the HIPPI Source device is provided
to the Source Host by the STATUS/CONTROL
interface, which allows the Source Host to control the
device clock frequency and phase (if necessary), and
to select the operating mode of the Source device.
50_MHZ (input) [50MHZ]
This 50 MHz TTL clock is divided by 2 to generate a
50% duty cycle 25 MHz clock for all internal timing
functions of the Source device and as the generated
and transmitted HIPPI channel CLOCK signal. This
*The active state of MODE_SELECT_2 is used for manufacturing test of
the Source device.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
