S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
SOURCE FIFO CONTROL
HIPPI DATA CONTROL SIGNALS
SHORT_BURST PACKET_AVAILABLE
When a data transfer is enabled, the Source device
will initiate read operations of the Source Host FIFO
by activating the Source FIFO control lines.
(input) [SHBST]
(input) [PKTAV]
IDLE. No
PACKET or
BURST onto
HIPPI channel
0
0
The Source FIFO control signals are:
READ_CLOCK (output) [RDCLK]
Assert PACKET
onto the HIPPI
channel*
This signal is a continuous 25 MHz clock synchronous
with the internal clocks of the Source device and the
HIPPI channel differential ECL CLOCK signal. The
signal is intended to be used together with NREN to
control the read function of the FIFO and as a
reference for timing critical Host-side control signals
such as SHORT_BURST and PACKET_AVAILABLE.
This signal is intended to drive the ‘read clock’ input
of the Source Host FIFO system.
0
1
1
1
0
1
Associated data
is a HIPPI
I-Field
Associated data
is last word of
HIPPI Burst
When the Source Host initiates a HIPPI
CONNECT_REQUEST, the Source device performs
read operations until a HIPPI I-Field is read. The
Source device recognizes a HIPPI I-Field by
decoding the HIPPI data control lines. Once a HIPPI
I-Field is presented to the Source device, the
REQUEST line will be asserted on the HIPPI
channel and the I-Field will be put on the HIPPI
channel data bus. By identifying the HIPPI I-Field in
this way, the Source Host can effectively queue
several connections in the FIFO and also enter
primary and secondary I-Fields for single connections
to support alternate paths for connect reject retries.
NOT_READ_ENABLE (output) [NRDEN]
This signal when held low, is used to strobe data
from the FIFO to the Source device. This signal is
used as a gate of the 25 MHz TTL RDCLK for the
synchronous operation of the FIFO. This signal is
intended to drive the ‘read enable’ input of the
Source Host FIFO system.
HIPPI DATA CONTROL
PACKET_AVAILABLE (input) [PKTAV]
This signal when high causes the Source device to
start a Packet if Bursts are available. When brought
low, this signal will end the Packet.
When data transfers are enabled, as described
above, the HIPPI data control field specifies what
partitioning operations are to be performed by the
Source device on the associated data word. The
main partitioning operations are: begin HIPPI
Packet, maintain HIPPI Packet, terminate HIPPI
Packet, auto-burst termination, and explicit (short)
burst termination.
SHORT_BURST (input) [SHBST]
This signal when high while PACKET_AVAILABLE is low
indicates presence of I-Field data at the Source device
input data lines. During a Burst, a high level indicates that
the current data word is the last word of a Short Burst.
Each read operation performed by the Source device
reads a Data/Parity word, and an associated HIPPI
data control field consisting of the PACKET_AVAILABLE
and SHORT_BURST signals. Because the HIPPI
data control field is to be read in parallel with the
associated DATA and PARITY, these (two) bits can be
written by the Source Host into the Source Host FIFO
as the DATA and PARITY are transferred into it. As the
Source device reads each word from the Source Host
FIFO, the HIPPI data control field specifies what type
of HIPPI data operation is to be performed.
The three HIPPI Packet functions control the
organization of data into HIPPI Packets. The auto-
burst termination allows the Source device to
automatically delimit the unbounded data from the
Source Host FIFO into HIPPI Bursts of 256 (max)
words each. The Short Burst termination allows the
Source Host to specify BURST boundaries for HIPPI
data bursts. In addition to the explicit Short Burst
and auto-burst terminations, the Source device will
terminate a HIPPI Burst if the HIPPI Packet is
terminated at a non-256 word boundary or if the
Source Host supply of data expires on a non-256
word boundary.
The three basic types of HIPPI data operations are:
I-Field, HIPPI PACKET control, and HIPPI BURST
control. The HIPPI data control signals defining these
data types are shown on the HIPPI Data Control Table.
*The Source device will not assert Packet onto the HIPPI channel until the first
data Burst of the Packet is sent. This prevents the possible generation of a zero-
Burst Packet (illegal) onto the HIPPI channel.
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
