S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 4. Typical HIPPI-PH Waveforms
The circuits provide diagnostic modes for testing the
devices themselves plus the circuitry that interfaces
to the device. In the self-test modes, the INTER-
CONNECT signal can be deasserted. This
effectively “unplugs” the device undergoing self-test
from the HIPPI channel making it unavailable for
connection and thus unable to generate spurious data
or control information while in the diagnostic mode.
REQUEST (S)
CONNECT(D)
READY (D)
PACKET (S)
BURST (S)
DATA BUS (S)
S2020 HIPPI SOURCE DEVICE
I-Field Data LLRC Data LLRC
Data LLRC
Burst
This device meets the signalling protocol requirements
for a HIPPI-Source; i.e., it controls the forward signals
and receives and acts on the reverse signals.
Burst
Burst
Source: ANSI X3.183–1991
High-Performance Parallel Interface.
Mechanical, Electrical, and Signalling
Protocol Specification (HIPPI-PH).
The Host-side consists of 45 single-ended TTL inputs
used for data, control and the 50 MHz clock as well
as 9 single-ended TTL outputs used for control of
the external FIFO and to obtain device status.
The Host systems are the actual originator and the
ultimate destination of the data sent over the HIPPI
channel. The purpose of the S2020 and S2021 is to
decouple the Host hardware and software from the
timing and formatting details of the interface. Each
circuit can be considered as having a “Host-side”
and a “HIPPI-side.” The Host-side of the Source
circuit accepts data from the Host FIFO and passes
it to the HIPPI-side. The HIPPI-side controls the
forward signals (REQUEST, PACKET, BURST and
CLOCK) and receives the reverse signals (CONNECT
and READY) of the HIPPI channel. The HIPPI-side of
the Destination circuit receives the forward signals
and controls the reverse signals of the HIPPI
channel. The Host-side of the Destination delivers
the received data to the Host FIFO.
The HIPPI-side consists of 40 differential ECL
outputs (forward signals), 2 differential ECL inputs
(reverse signals), 1 single-ended TTL output
(Source-to-Destination INTERCONNECT signal) and
1 single-ended ECL input (Destination-to-Source
INTERCONNECT signal).
ELECTRICAL REQUIREMENTS
The differential ECL outputs require eighty 330 Ohm
2% resistors, one per pin. The differential ECL inputs
require two 110 Ohm 2% resistors, one per input pair.
The two INTERCONNECT signals require external
transmit and receive networks to reliably implement the
signal swing required by the HIPPI Specification. For
the Source-to-Destination INTERCONNECT (output
signal), the required network is shown in Figure 10.
The Host-side of both circuits can be thought of as
consisting of four sections:
It should be noted that this network is only required if
switching control of the INTERCONNECT signal by
the Source device is desired. The network may be
omitted and a simple pull-down of the Source-to-
Destination INTERCONNECT via a 220 Ohm resistor
to Vee may be used as indicated in the ANSI standard.
For the Destination-to-Source INTER-CONNECT (input
signal), the required network is shown in Figure 11.
• Connect Control (for connecting/disconnecting
to/from the HIPPI channel)
• Data/FIFO Control (for moving data to/from the
Host logic)
• Data + Parity (for presenting data to/from the
Host logic
• Status/Control (for general control of the circuit
and to obtain status from the circuit)
The network is strongly recommended for use on the
received INTERCONNECT signal to avoid risk of
saturation when operated with a switchable INTER-
CONNECT Destination device such as the S2021. It
is also recommended for use in the non-switched
passive pull-down applications to avoid damage to the
ECL input due to transients caused by mechanical
connection/disconnection cycles of the allowed cabling
while Source and Destination are under power.
The purpose of these circuits is to reduce the
complexity of the circuitry required to mate a Host
memory system to the HIPPI channel. The Host-side
is primarily single-ended TTL while the HIPPI-side is
primarily differential ECL. Beside meeting the
signalling protocol requirements of the HIPPI
standard, the circuits provide a reduction of the
signal lines to the host interface.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
