S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 7. SYNC/RESYNC Block Diagram
SYNC
DATA
Rank 0
SYNC
REGISTERS
and
Raw Data
Rank 1
Rank 2
Rank 3
HIPPI
INTERFACE
HIPPI
RESYNC
REGISTERS
Channel Clock
Signals
LATCHES
Sync Indicator
Resync Select
Local Clock
Rank
PHASE
GENERATOR
SYNC
CONTROL
Select
Local
Clock
Phase Select
PHASE
DETECTOR
PHASE
CONTROL
Resync
Phase Adjust
Sync Error
HIPPI State — Packet/Burst
phase error is re-zeroed during the inter-burst/packet
Wait period by resynchronization. Since multiple
nodes could be in the channel between the
originating Source and the final Destination, the
inter-burst Wait states may have been “consumed”
before the data is received. The large phase
tolerance of the synch/resynch circuitry (shown in
Figure 7) in the Destination device allows 48
consecutive Bursts with missing Wait states to be
received before synchronization is lost. A maximum
rate transfer through a chain of 30 nodes, all with
worst-case jitter, operating at progressively worse
frequency margins, and all requiring a ‘dropped’
cycle at the same time would be required between
the originating Source and the final Destination to
produce 48 consecutive missing Wait cycles.
This network is only required if switching control of
the INTERCONNECT signal by the Destination
device is desired. The network may be omitted and a
simple pull-down of the Destination-to-Source
INTERCONNECT via a 220 Ohm resistor to Vee
may be used as indicated in the ANSI standard. For
the Source-to-Destination INTERCONNECT (input
signal), the required network is shown in Figure 11.
CONNECTION LATENCY
The connection latency through the Destination
device consists of two parts:
1) the time between the arrival of the REQUEST
signal on the HIPPI channel from the Source device,
to the presentation by the Destination device of the
I-field to the TTL data lines and assertion of
CONNECT_REQUEST ranges from 4 to 5 clock
cycles;
ELECTRICAL REQUIREMENTS
The resistors needed to complete the electrical
requirements of the HIPPI-Destination interface are
four 330 Ohm 2% resistors, one per pin of differential
ECL outputs, and forty 110 Ohm 2% resistors, one per
pair of differential ECL inputs
2) the time between assertion of CONNECT_IN signal
by the host (to accept the connection request), to the
assertion of the CONNECT signal by the Destination
device on the HIPPI channel is 2 clock cycles.
The two INTERCONNECT signals require external
transmit and receive networks to reliably implement
the signal swing required by the ANSI standard. For
the Destination-to-Source INTERCONNECT (output
signal), the required network is shown in Figure 10.
The Destination device connection latency therefore
ranges from 6 to 7 clock cycles. This does not include
local host connection processing (the time it takes the
host to decide whether or not to accept a particular
connection request).
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
