S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Burst counter contents will result in that same
difference between the READY and Buffer counters.
When a subsequent HIPPI connection is accepted, the
Destination FLOW control circuit will automatically
send the correct number (equal to the number of
currently available buffers in the Destination Host) of
READY pulses.
DESTINATION FLOW CONTROL
After a HIPPI connection is established, data transfer
from the Source Host to the Destination Host is
enabled by the presence of data from the Source Host
and the current ability of the Destination Host to accept
that data. Although this function is performed at the
HIPPI Source, the HIPPI Destination signals its current
buffer capacity to the Source via the READY signal on
the HIPPI channel.
The Destination FLOW control signals are:
READY_IN (input) [RDYIN]
This input controls the Destination FLOW control
circuit’s Buffer and READY counters. A rising edge on
this input will increment the Buffer counter and, if a
Connect Request has been accepted, generate a
READY pulse on the HIPPI channel as well as
increment the READY counter by one. This input can
be driven by a free-running 12.5 MHz clock for
maximum throughput on the HIPPI channel (repre-
senting infinite Host buffer capacity), or it can be
controlled by the Host memory system. If controlled by
the Destination Host system, after initialization with one
edge for each available buffer, the Host may generate
one rising edge on this input after it processes and
releases each used 256 word buffer.
The Destination FLOW control circuit consists of a set
of modulo 64K counters that maintains the current
Buffer capacity, the number of READYs sent to the
HIPPI Source, and the number of Bursts received from
the HIPPI Source. At initialization (Destination device
reset) all of these counters are reset. When the
Source-to-Destination INTERCONNECT [SDIC] signal
is true and the Destination device is in a functional
mode, the Destination Host may initialize the Buffer
counter to the number of HIPPI Bursts that it can
accept. When a Connect Request is accepted, the
Destination device will automatically generate legal
READY pulses and increment the READY counter for
each pulse until the READY counter equals the Buffer
counter. If the Buffer counter was not initialized before
the Connect Request, then no READY pulses will be
generated. If the Buffer counter is incremented after
the Connection is made, then READY pulses will
automatically be generated until the READY and Buffer
counters are equal. The Buffer counter will be disabled
when it equals Burst count -1, thereby putting a limit of
64K on the number of pending READY pulses.
NOT_RESET_READY (input) [NRRDY]
This signal is an active low TTL input that erases the
stored count of available Host system buffers by
resetting the Buffer, Ready and Burst counters to
their initial states.
DESTINATION FIFO CONTROL
When a data Burst is received over the HIPPI
channel, the Destination FIFO Control provides the
signals necessary to transfer the received data from
the Destination device to the Destination Host FIFO
system. In addition to transferring received data
Bursts, the Destination device will also transfer the
HIPPI I-Field, and the channel and device status
words as specified in the FIFO Control Signal Table.
To provide flexibility at this interface, the Destination
device identifies each type of information presented
to the Destination Host, so that each implementation
may customize its use of the information.
If the Burst counter is not equal to the READY counter
as a data Burst is received, then the Burst counter is
incremented and the data is automatically transferred
to the Destination Host. If the Burst counter is equal to
the READY counter as a data Burst is received, then
the data is not transferred to the Destination Host and
an Overflow error is reported.
When the HIPPI connection is terminated, one of two
operations may be performed by the Destination Host:
the Destination FLOW control counters may be reset
(and initialized), or the current buffer capacity may be
automatically saved for the next HIPPI connection. To
reset and initialize, the Destination Host must maintain
a set of buffer counters, or empty the buffers before the
next connection. To automatically save the current
buffer capacity, the Destination device will initialize the
READY counter to the Burst counter: at the end of a
HIPPI connection, the number of remaining available
buffers at the Destination Host is the difference
between the Burst counter and the Buffer counter.
Therefore, initializing the READY counter to the
The Destination FIFO Control signals are:
WRITE_CLOCK (output) [WRCLK]
This signal is a buffered 25 MHz TTL clock
synchronized to the internal local clock. It is intended
for use with the VALID signal to transfer data to the
write port of the FIFO and to serve as the timing
reference for critical input and output control signals
of the Host-side of the Destination device.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
