S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
CONNECT_OUT (output) [CNOUT]
The Source device FLOW control circuit consists of a set
of 16-bit counters that automatically maintain the number
of READYs received from the HIPPI Destination and the
number of BURSTs sent to the HIPPI Destination. In
the Source device, these counters are reset when the
HIPPI channel is disconnected, and then enabled
when the HIPPI channel is reconnected. When the
BURST counter and the READY counter are equal,
data transfer will be disabled and both counters are
enabled. When the BURST counter and the READY
counter are not equal and their difference is not 65535
[(2exp16)-1], data transfer will be enabled and both
counters are enabled. When the difference between
the BURST counter and the READY counter is 65535,
data transfer is enabled and the READY counter is
disabled. Disabling the READY counter results in a limit
of 65535 pending READYs for the HIPPI connection.
This signal, along with the CONNECT_REQUEST
and ACCEPT/REJECT signals defines the current
state of the HIPPI connection. A high level indicates
active acceptance or rejection of a requested
connection.
ACCEPT/REJECT (output) [ACREJ]
This signal along with the CONNECT_REQUEST
and CONNECT_OUT signals defines the current
state of the HIPPI connection. A high level indicates
active acceptance of a requested connection.
SEQUENCE_ERROR (output) [SQERR]
This signal when high indicates the presence of
either a Source error state (PACKET_AVAILABLE
dropped before the first word of Burst transmitted or
CONNECT_REQUEST is reasserted before Destin-
ation has deasserted CONNECT) or Destination
error state (CONNECT is detected before REQUEST
has been asserted).
The Source FLOW control signals are:
BURST_AVAILABLE (input) [BSTAV]
This signal when held high enables the initiation of a
data transfer from the FIFO, through the Source
device, to the HIPPI channel. When held low this
signal prevents the initiation of a data transfer. A
transition from high to low after a data transfer has
been initiated has no effect on that transfer (i.e., the
current Burst will terminate normally).
SOURCE_NOT_DESTINATION (output) [SRNDS]
This signal is used to distinguish between a Source
error (logic 1 state) and a Destination error (logic 0
state).
DATA/FIFO CONTROL
This interface provides control to the Source Host
system, of the flow and organization of the data to be
transferred over the HIPPI channel. It is intended for
this interface to attach to an external synchronous
FIFO, which is in turn attached to the Source Host
memory system. Recommended FIFO’s capable of
buffering 4 or more Bursts are:
DATA_AVAILABLE (input) [DATAV]
This signal when high indicates the current presence of
at least one more word from the Source Host FIFO and
enables the synchronous load of the data bus into the
Source device. When low this signal disables the data
loading. It is intended that this signal be driven by the
Not Empty flag of the FIFO. In this configuration any
interruption of the data flow due to the FIFO not being
refilled by the host will result in a Short Burst with
normal LLRC and Burst termination. This signal must
be reasserted and the BURST_AVAILABLE signal
reasserted to start a subsequent Burst.
IDT P/N 72225LB20 1K x 18 bits
IDT P/N 72235LB20 2K x 18 bits
IDT P/N 72245LB20 4K x 18 bits
The signals of this interface can be divided into three
groups; Source FLOW control, Source FIFO control,
and HIPPI data control.
DATA_REQUEST (output) [DTREQ]
SOURCE FLOW CONTROL
This signal indicates the current ability of the HIPPI
Destination to accept data. When high the signal
indicates a current connection on the HIPPI channel
and the inequality of the BURST and READY
counters in the Source device FLOW control circuit.
When low, (and during a HIPPI channel connection)
the signal indicates the equality of the BURST and
READY counters in the Source device FLOW control
circuit, i.e., the Source has sent one BURST to the
HIPPI Destination for each READY received from
that Destination.
After a HIPPI connection is established, data
transfer from the Source Host to the Destination
Host is enabled by the presence of data from the
Source Host and the current ability of the Destination
Host to accept data. The presence of data from the
Source Host is indicated to the Source device on the
Source FLOW control lines. The ability of the
Destination Host to receive data is determined by
the Source device’s FLOW control circuit.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
