S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 6. HIPPI Destination Block Diagram
HIPPI-side
Host-side
source available
connect request
connect in
accept/reject
32 data + 4 parity
request
Connect
Control
burst out
packet out
packet
burst
Data/
FIFO
Control
ready in
not reset ready
clock
HIPPI
Dest.
data valid
write clock
32 data + 4 parity
Rx parity error
Signals
connect
ready
Rx LLRC error
Data
sync error
mode select 0
mode select 1
mode select 2
25 MHz
50 MHz
Select 0
Select 1
Select 2
Status/
Control
interconnects
85 ECL, 1 TTL
57 TTL
S2021 HIPPI DESTINATION DEVICE
and thus verify the integrity of the DATA, PARITY,
and DATA/FIFO CONTROL busses. This test routine
continues until the Mode is changed or until a mis-
compare is detected between the Host’s expected
LLRC and the device’s generated LLRC. When a
mis-compare is detected, the simulated connection
is terminated and CONNECT_OUT is deactivated.
Mode 0 (reset) clears the board test mode.
This chip meets the signalling protocol requirements
for a HIPPI-Destination, i.e., it controls the reverse
signals and receives the forward signals.
The HIPPI-side consists of 40 differential ECL inputs
(forward going signals), 2 differential ECL outputs
(reverse signals), 1 single-ended ECL input (Source-
to-Destination INTERCONNECT signal), and 1
single-ended TTL output (Destination-to-Source
INTERCONNECT signal).
Mode 2 (10) is the WAIT mode. This mode provides
an interlock device between the Source Host and the
HIPPI channel that requires the Source Host to
acknowledge an inactive Destination-to-Source
INTERCONNECT [DSIC] before an active DSIC
signal is processed. In this mode the Source-to-
Destination INTERCONNECT [SDIC] is active. The
requirement upon the Source Host is that if
DESTINATION_AVAILABLE is inactive and the
Source Host is waiting for it to become active, the
Source device must be put into Mode 2. Once
DESTINATION_AVAILABLE is active, the Source
device must be put into Mode 3 to initiate further
operations.
The Host side consists of 45 single-ended TTL
outputs used for data, FIFO control and status, 9
single-ended TTL inputs used for chip control, a 25
MHz clock and a 50 MHz clock and 3 TTL
Bidirectional I/O.
In addition to the signal translation and control
handshake functions, the Destination device
provides a four stage “elastic store” for the buffering
of the data, parity, and control information received
from the HIPPI channel. This internal FIFO (not to be
confused with the external multi-Burst size FIFO)
together with a digital phase locked loop structure
allow the HIPPI channel clocked information to be
synchronized to the local (Host-side) 25 MHz clock.
The use of the combined 50 MHz and 25 MHz clocks
allow tracking of the synchronizer through more than
1200 degrees of phase “slip” or error between
received HIPPI clock and the local clock. In a
normally operating HIPPI channel, the accumulated
Mode 3 (11) is the operational mode. This mode
activates the Source-to-Destination INTERCONNECT
signal and enables the functional operation of all the
Source device interfaces.
NOTE: The only time DESTINATION_AVAILABLE will go from inactive to
active is if Destination-to-Source INTERCONNECT is active while the
Source device is brought from Mode 0 (reset) to Mode 3 (operational) or if
the Source device is in Mode 2 (wait).
8
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
