S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 5. HIPPI Source Block Diagram
Host-side
HIPPI-side
destination available
32 data + 4 parity
connect request
connect cut
accept/reject
Connect
Control
request
packet
short burst
packet available
burst available
data request
read clock
not read enable
data available
burst
Data/
FIFO
Control
HIPPI
SOURCE
SIGNAL
clock
connect
32 data + 4 parity
input parity error
Data
ready
mode select 0
mode select 1
mode select 2
50 MHz
Status/
Control
sequence error
interconnects
Source Not Dest.
54 TTI
85 ECL, 1 TTL
CONNECTION LATENCY
SOURCE CONNECT CONTROL
The Connection latency through the Source device
consists of two parts: 1) The delay from the rising
edge of the TTL input CONNECT_REQUEST to the
assertion of the REQUEST signal in parallel with the
placement of the I-Field data on the Host data bus
and its availability on the HIPPI channel data bus (4
clock cycles), and 2) the delay from the detection of
the CONNECT signal for the 17th clock cycle and
the assertion of the TTL outputs CONNECT_OUT
and ACCEPT/REJECT to the Host (3 to 4 clock
cycles). The total connection latency in the Source
device ranges from 7 to 8 clock cycles. This does
not include cable delay or Destination processing.
Connection control is provided by four control signals
and two error flags on the Host-side of the Source
device. Using the signals the Host can “request” a
connection to a Destination and monitor the results
(whether the Destination has accepted or rejected the
connection request). Timeout mechanisms, if required,
must be provided by the Host hardware or software.
DESTINATION_AVAILABLE (output) [DSTAV]*
A high level on this signal indicates an active
Destination-to-Source INTERCONNECT signal. Low
indicates inactive INTERCONNECT.
CONNECT_REQUEST (input) [CNREQ]
This signal when high directs the Source device to
read the I-Field from the Host System (see HIPPI
Data Control, page ). When a valid I-Field is read, it
is placed on the HIPPI channel and the HIPPI
REQUEST signal is asserted. The information in the
I-Field can be used by intermediate HIPPI nodes
(nodes that are not end-points) to control the routing
of the associated connection. The Host would then
monitor the CONNECT_OUT and ACCEPT/REJECT
signals to determine the state of the connection.
DATA LATENCY
The data latency through the Source device is
defined as the delay from the rising edge of the
BURST_AVAILABLE signal and the assertion of the
BURST signal on the HIPPI channel. The data
latency is 4 clock cycles. This does not include cable
delay or Destination processing.
*Bracketed signal name refers to pin matrix on pages 20–23 (all signals).
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
