S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Once the connection is established, data transfer
can proceed according to the Physical Framing
HIPPI OVERVIEW
The individual HIPPI channel is a simplex interface,
meaning that data moves in one direction from the
HIPPI Source (S2020) to the HIPPI Destination
(S2021). Thus a fully bidirectional interface requires
the use of two HIPPI channels as indicated in the
System Block Diagram.
Hierarchy (see Figure 3). The basic data block is the
Burst consisting of from 1 to 256 words of 32 data
bits and 4 bits of odd byte parity. Each Burst is
delimited by the assertion and deassertion of the
BURST signal by the data Source. Every burst is
followed immediately by Length/Longitudinal Redun-
dancy Checkword (LLRC) which is the even parity
for each bit for the entire length of the Burst together
with the modulo 256 count of the number of words in
the Burst. The count is included in the parity
calculation for the least significant 8 bits of the LLRC
word. For the normal full burst of 256 words, the
count is all zeros (256 base 2 truncated to 8 bits).
Figure 2. System Block Diagram
S
2
0
2
0
S
2
0
2
1
HIPPI
HIPPI
FIFO
FIFO
FIFO
FIFO
HOST
MEMORY
SYSTEM
HOST
MEMORY
SYSTEM
S
2
0
2
1
S
2
0
2
0
Figure 3. Physical Framing Hierarchy
Disabled I-Field Connection
Packet
LLRC
Packet
Wait
Packet
The transfer of data from the Source to the
Destination depends on the physical connection of
the two endpoints and the exchange of requesting,
acknowledging, and data delimiting signals. The
Source and Destination circuits both observe the
state of the INTERCONNECT signals to verify a
physically intact channel. If both Source and
Destination are interconnected, the Source may
initiate a data transfer by asserting the REQUEST
signal. At the same time the Source places a 32 bit
word also known as the I-Field on the data lines
together with the appropriate Byte parity. The Upper
Level Protocols (ULPs) controlling the Source and
Destination may use this information for routing. The
Destination responds to the REQUEST by asserting
the CONNECT signal either for a short period while
leaving the READY signal inactive to actively reject
the REQUEST, or by asserting CONNECT and then
asserting the READY signal to accept the REQUEST
and indicate the availability of an input data buffer.
The Destination can also accept the REQUEST by
asserting CONNECT for a longer period without
sending a READY, thus indicating a temporary delay
in the availability of an input data buffer. The Source
may remove the I-Field data after detecting the
CONNECT signal.
Wait Burst
Wait Burst LLRC Wait Burst LLRC
256 words of 32 bits each
Source: ANSI X3.183–1991
High-Performance Parallel Interface.
Mechanical, Electrical, and Signalling
Protocol Specification (HIPPI-PH).
One or more Bursts are grouped as a Packet
delimited by the assertion and deassertion of the
PACKET signal by the Source. Wait periods are
placed between Bursts and between Packets to
allow synchronization adjustments between the
Source and Destination circuits. A connection may
contain one or more Packets. The details of the data
transfer handshake are shown in Figure 4.
S2020 AND S2021 DESCRIPTION
The S2020 Source and the S2021 Destination
circuits generate all of the required control and
handshaking signals described above in the correct
timing relationships, as well as providing Burst and
Packet control, READY to BURST coordination, and
LLRC generation and checking.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
