QT2022/32 - Data Sheet: DS3051
The TX Fiber Output derives timing from a 156.25MHz reference applied at EREFCLK or an alternate reference
applied at TXPLLOUT. When applying an alternate reference to TXPLLOUT, the TXPLLOUT output driver must be
disabled using MDIO bit 1.C001h.3. Selection of the desired reference is determined by the state of MDIO bit
1.C001h.7. Refer to Table 7 on page 35 for details. The TX PLL generates a 10 GHz clock from the reference by
multiplying the frequency. The TX PLL output provides a clock for the TX Fiber Processing Block and Outputs.
The RX Fiber CDR locks to the received signal and generates a recovered clock. The recovered clock provides
timing to the RX Fiber Processing Block. When a SYNCERR is generated, the RX Fiber Input CDR will lock to the
reference applied to the selected reference, either EREFCLK or TXPLLOUT, to pull the frequency back to nominal.
Once the SYNCERR has cleared, the CDR will attempt to lock to the RX Fiber Input signal.
The RxXAUI Outputs derive timing from the TX PLL. The RX PLL generates the 3.125 GHz clock from a reference
from the TX PLL. The RX PLL output provides a clock for the RX XAUI Processing Block and Outputs.
For each TxXAUI Input, a CDR locks to the received signal and generates a recovered clock. The recovered clock
from lane 1 (TxXAUI1) provides a clock for the TxXAUI Processing Block.
Transfer of data across clock boundaries along each data path is accomplished through rate compensation blocks.
6.1.2 Forced Line Timing Mode
The Forced Line Timing mode forces the TX Fiber Output to derive timing from the RX Fiber Input recovered clock.
The Forced Line Timing mode is useful for various test scenarios or implementations where the timing is controlled
externally. Forced Line Timing is controlled by MDIO register bit 1.C001h.9.
6.2 WAN Application Timing Modes (QT2032 Only)
This section describes additional timing modes supported only by the QT2032. The timing paths through the
QT2032 vary depending upon the mode of the device. Some modes that affect these paths include:
1. Fiber Interface Mode: either LAN or WAN, see Section 8.3.1 on page 59.
2. VCXO PLL Mode: enabled or disabled, see Section 6.2.4 on page 32.
3. Line Timing Mode: Disabled, Automatic, or Forced, see Section 6.2.2 on page 30.
In order to understand the relationship between timing reference and the behavior of input and output signals it is
important to understand the general timing architecture of the QT2032. In the following sections, the timing archi-
tecture in the WAN mode is explained.
6.2.1 Timing Architecture in WAN mode (QT2032 Only)
In WAN mode, each quadrant TxXAUI, RxXAUI, RX Fiber, and TX Fiber is independently timed. The typical timing
architecture and timing paths in WAN mode are illustrated in Figure 5. An optional configuration in VCXOONLY
mode (VCXOB = 0 and VCXOONLY = 1) where the VCXO can provide a reference frequency is also illustrated in
Figure 7.
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