QT2022/32 - Data Sheet: DS3051
Figure 3: Transmit Scrambler
Serial Data Input
S0
S1
S2
S38
S40
S56
S57
Scrambled Data Output
5.1.8 Gear Box
The gear box converts the data from a 66 bit wide data bus at 156.25 Mb/s to a 64 bit wide bus at 161.1328 Mb/s.
This step is required to prepare the data for serialization in the next functional block.
5.1.9 Transmit WAN Interface Sublayer (WIS) (QT2032 Only)
The TX WIS block accepts data from the gear box and maps it into the payload of the transmitted STS-192C WIS
frame stream. Fixed stuff octets are added, together with a set of Path Overhead octets, to create a Synchronous
Payload Envelope (SPE). Line and Section Overhead octets are combined with the SPE and then scrambled using
the frame-synchronous scrambler to produce the final transmitted WIS frame. The WIS continuously generates
one WIS frame every 125μs.
5.1.10 Transmit Multiplexer and Clock Generation
A clock divider generates the clock frequencies required to multiplex the 64 bit wide bus coming from the TX WIS
into a single 10Gb/s output, from the locally generated 10GHz clock.
5.1.11 Output Data Driver
The output driver has a nominal output voltage of 250 mVpp per side. TXOUTN and TXOUTP are both terminated
on chip with 50Ω to 1.2V. The output level can be adjusted via an external resistor connected to TXLEVEL. The
output polarity can be inverted by pulling pin TXOUT_SEL high.
5.1.12 Line Timing Mode
Line timing is used in the QT2032 to ensure the transmitted data is synchronized to the SONET network. In line
timing mode, the reference clock used for the transmit PLL is derived from the recovered receive clock. Line timing
mode is enabled by the Line Timing Control Register. Please see Section 6, “Datapath Clocking,” on page 26 for
details.
Line timing is not supported in the QT2022.
Revision 5.11
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