QT2022/32 - Data Sheet: DS3051
Automatic Line Timing Mode
The Automatic Line Timing mode allows the TX Fiber Output to derive timing from a valid recovered clock from the
RX Fiber Input. When the RX Fiber Input is not valid, the TX Fiber Output derives timing from SREFCLK (or from
VCXOI in VCXOONLY mode). The QT2032 deems the recovered clock from the RX Fiber Input to be valid when all
of the following conditions are TRUE:
1. RX Fiber CDR VCO is not in forced mode (MDIO 1.C030h.10 = 0)
2. Fiber Interface is not in PMA System Loopback (MDIO 1.0.0 = 0)
3. PMA LOS defect is clear RXLOSB_I = 1 (visible in MDIO 1.10.0) or LOS Override is Set (MDIO 1.C001h.10 =
1). This condition assumes that XFP = 0. If XFP = 1 then the RXLOSB_I is inverted.
4. PMA SYNCERR unlatched defect is clear (latched version visible in MDIO register 1.C001h.1) or SYNCERR
Override is Set (MDIO register 1.C030h.5:4 = ‘01’)
5. WIS LOF unlatched defect is clear (latched version visible in MDIO register 2.33.7) or LOF Override is Set
(MDIO register 1.C030h.15)
6. WIS Line AIS unlatched defect is clear (latched version visible in MDIO register 2.33.4) or AIS Override is Set
(MDIO register 1.C030h.14)
For each defect used to disable line timing, an override capability is provided. By default, the override for each
defect is Clear. However, the override for each defect may be independently set to prevent the associated defect
from disabling line timing. The effective logic used to generate the internal signal enabling line timing, ltimeok, is
represented in Figure 8.
Figure 8: Line Timing Enable Logic
unlatched_WIS_line_ais
mdio_autoltime
(1.C001h.14)
mdio_line_ais_override (1.C030h.14)
unlatched_sync_err
mdio_syncerr_override (1.C030h.7)
ltimeok
(enables linetiming)
mdio_frcltime
(1.C001h.9)
core_frcvco_frx (1.C030h.10)
pma_sys_lpbk (1.0.0)
unlatched_WIS_loss_of_frame
mdio_lof_override (1.C030h.15)
RXLOSB_I
XFP
mdio_los_override (1.C001h.10)
(loss_of_signal)
(xor)
(note MDIO bits are low by default i.e. on powerup)
Further qualification of the signal may be required by external software. For example, it must be determined
whether the use of the received signal as a line timing reference will result in a timing loop. This may happen if the
far end is also in line timing mode. Qualification of the received signal may be achieved using the Synchronization
Status Message (SSM) in the WIS S1 byte. Refer to section Section 7.3.3 on page 47.
Revision 5.11
AppliedMicro - Confidential & Proprietary
31
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
