QT2022/32 - Data Sheet: DS3051
5.2 Receive Path
5.2.1 Limiting Amp
The receiver input contains a limiting amplifier designed for a differential CML voltage across the RXIN inputs. The
input polarity can be selected by pin RXIN_SEL. The input sensitivity is good enough to eliminate the need for an
external limiting amp in many applications. For a system card application, the XFP input pin is set high and an input
equalization circuit is activated to allow for longer FR4 traces. It can be deactivated by asserting MDIO register bit
1.C030h.6.
AC coupling of the 10Gb/s input signal(s) is required to achieve good sensitivity as it reduces the amount of 1/f
noise at the input to the QT2022/32.
5.2.2 Loss of Signal Detector
The RX input limiting amplifier also incorporates a loss of signal detector. The loss of signal detector is disabled if
the input equalization circuit is activated (see Section 5.2.1 above). The LOSOUTB signal is available as an output.
The loss of signal threshold (in mVpp) is controlled by adjusting the value of the external resistor connected to the
ITH_LOS pin. The threshold includes built-in hysteresis to prevent LOSOUTB chatter. The LOSOUTB signal can
be externally connected to the RXLOSB_I input (this allows for the option of using an external TIALA with its own
loss of signal detector).
5.2.3 Clock Recovery
The output of the limiting amp goes to a clock and data recovery (CDR) circuit. When the PLL is frequency locked
to the incoming data, the internal signal, frxlock is asserted. When frxlock is low the receive data outputs RxX-
AUI<0:3> will transmit idle frames and error codes. The state of frxlock is reflected in the ‘PMA receive link status’
bit, 1.1.2, a latched low register bit whose value is determined by the equation {frxlock AND RXLOSB_I}. The state
of the RXLOSB_I input is shown separately in Register bit 1.10.0.
The PLL uses an external loop filter. See Section 18.1, “External Components,” on page 209 for the loop filter com-
ponents and values.
Recovered Clock Frequency Monitoring and RXCLK
When the receive recovered clock is more than 500ppm from the transmit reference clock, a synchronization error
is declared and the internal signal sync_err goes high. sync_err can be viewed at MDIO register 1.C001h.1. This is
a latched high register bit that is cleared on read. On powerup or reset, the register must be read to clear it.
5.2.4 Demultiplexer and Clock Divider
All clocks needed for the demultiplexer and the reset of the receive path are generated in this block by dividing
down the 10GHz recovered clock. The demultiplexer converts the 10 Gb/s serial incoming data into 64 parallel bits.
A divide-by-64 recovered clock can be output at RXPLLOUT by setting MDIO register bit 1.C001h.6 = 1.
5.2.5 Receive WAN Interface Sublayer (WIS) (QT2032 Only)
The RX WIS block receives data from a SONET link and extracts the Ethernet payload from the STS-192c SPE. It
also monitors the integrity of data at the Section, Line and Path levels and monitors both near and far end faults.
The WIS receive and transmit blocks can be bypassed by setting MDIO register 2.7.0 to 0 or if LANMODE = 1.
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