QT2022/32 - Data Sheet: DS3051
Figure 6: WAN Mode Timing with Fixed Frequency Reference
Coarse control voltage
used to center CDR VCO
tuning range.
TX XAUI
TX Data Path
Inputs
TxXAUI0P/N
CDR
CDR
CDR
CDR
TxXAUI1P/N
TxXAUI2P/N
TxXAUI3P/N
TX Fiber Output
TXOUTP/N
TX XAUI
Rate
TX Fiber
Processing
Compensation
Processing
VCXO PLL includes
external VCXO, op amp,
and filter components.
VCXO
PLL
TX
PLL
Fiber Interface
XAUI
Interface
RX
PLL
RX Fiber Recovered Clock
used for line timing.
RxXAUI2P/N
RxXAUI1P/N
RxXAUI2P/N
RxXAUI3P/N
RX XAUI
Processing
Rate
Compensation
RX Fiber
Processing
RX
CDR
RXIP/N
TX Fiber Input
Reference used to center
CDR VCO when input
signal is failed.
RX XAUI
Outputs
RX Data Path
EREFCLK
TXPLLOUT
SREFCLK
Timing Path
155.52 MHz
156.25 MHz
XO
or
622.08 MHz
XO
Coarse Control Voltage
28
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