QT2022/32 - Data Sheet: DS3051
Figure 7: WAN Mode Timing without Fixed Frequency Reference
Coarse control voltage
used to center CDR VCO
tuning range.
TX XAUI
TX Data Path
Inputs
TxXAUI0P/N
CDR
CDR
CDR
CDR
TxXAUI1P/N
TxXAUI2P/N
TxXAUI3P/N
TX Fiber Output
TXOUTP/N
TX XAUI
Rate
TX Fiber
Processing
Compensation
Processing
VCXO PLL includes
external VCXO, opamp,
and filter components.
VCXO
PLL
XAUI
Interface
TX
PLL
Fiber Interface
RX
PLL
RX Fiber Recovered Clock
used for line timing.
RxXAUI2P/N
RxXAUI1P/N
RxXAUI2P/N
RxXAUI3P/N
RX XAUI
Processing
Rate
Compensation
RX Fiber
Processing
RX
CDR
RXIP/N
TX Fiber Input
VCXO output used to
center CDR VCO when
input signal is failed.
RX XAUI
Outputs
RX Data Path
EREFCLK
TXPLLOUT
SREFCLK
Timing Path
156.25 MHz
XO
Coarse Control Voltage
The TX Fiber Output derives timing either from a 155.52MHz or 622.08MHz reference applied at SREFCLK (or
VCXOI when in VCXOONLY mode) or the received signal on the RX Fiber Input. The TX PLL generates a 10 GHz
clock from the selected reference by multiplying the frequency. The TX PLL output provides timing for the TX Fiber
Processing Block and Output. By default the TX PLL will lock to the reference applied at SREFCLK (or VCXOI
when in VCXOONLY mode), however it may optionally lock to the recovered clock from the RX Fiber CDR as
explained in Section 6.2.2 on page 30. In order to reduce phase noise from the selected reference and conse-
quently on the TX Fiber Output, an optional VCXO PLL may be used to filter phase noise on the selected
reference, as explained in Section on page 32.
The RX Fiber CDR locks to the received signal and generates a recovered clock. The recovered clock provides a
clock to the RX Fiber Processing Block and provides an optional reference for the TX Fiber Output. When the
recovered clock deviates by >500ppm from the reference clock, the RX Fiber Input CDR will then lock to the refer-
ence from SREFCLK (or VCXOI when in VCXOONLY mode) to pull the VCO frequency to nominal frequency. The
CDR will lock to the RX Fiber Input signal when the clock rate is <500ppm from the reference.
The RX XAUI Outputs derive timing from a 156.25 MHz reference applied at EREFCLK. The RX PLL generates the
3.125 GHz reference from the reference by multiplying the frequency. The RX PLL output provides a clock for the
RX XAUI Processing Block and Outputs.
For each TX XAUI Input, a CDR locks to the received signal and generates a recovered clock. The recovered clock
from lane 1 (TxXAUI1) provides timing to the TX XAUI Processing Block.
Transfer of data across clock boundaries along each data path is accomplished through rate compensation blocks.
Revision 5.11
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
