QT2022/32 - Data Sheet: DS3051
5.2.10 8B/10B Encoder
The data bus is divided into four 8-bit wide data channels. Each of the four channels has independent 8B/10B
encoders which will convert the 8 bit data lanes into 10 bit code words. Either a positive or negative disparity 10 bit
code word will be selected, depending on the running disparity.
5.2.11 Receive Multiplexer and XAUI Interface
After 8b/10b encoding has been added, the receive multiplexer serializes data words to form four 3.125Gb/s output
data lanes.The XAUI output drivers provide low-swing differential outputs with 100Ω differential output impedance
and are intended to be AC coupled. The 3.125 GHz timing is derived from the reference clock, EREFCLK.
6 Datapath Clocking
This section explains the clocking architecture and features of the QT2022 & QT2032.
6.1 LAN Application Timing Modes (QT2022 and QT2032)
6.1.1 Timing Architecture in LAN Mode
This section describes the timing of the QT2022. The QT2032 will follow this timing architecture when placed in
LAN mode.
In LAN mode, the RxXAUI and TX Fiber quadrants share timing references, but are generally independent of the
TxXAUI and RX Fiber quadrants. The timing architecture and timing paths in LAN mode are illustrated in Figure 5.
Figure 5: LAN Mode Timing (QT2022 and QT2032)
Coarse control voltage
used to center CDR VCO
tuning range.
TX XAUI
TX Data Path
Inputs
TxXAUI0P/N
CDR
CDR
CDR
CDR
TxXAUI1P/N
TxXAUI2P/N
TxXAUI3P/N
TX Fiber Output
TXOUTP/N
TX XAUI
Rate
TX Fiber
Processing
Compensation
Processing
Fiber Interface
TX
PLL
XAUI
Interface
RX
PLL
RX Fiber Recovered Clock
may be used as timing
reference. Test mode only.
RxXAUI2P/N
RxXAUI1P/N
RxXAUI2P/N
RxXAUI3P/N
RX XAUI
Processing
Rate
Compensation
RX Fiber
Processing
RX
CDR
RXIP/N
TX Fiber Input
Reference used to center
CDR VCO when TX Fiber
Input signal is failed.
RX XAUI
Outputs
RX Data Path
EREFCLK
TXPLLOUT
SREFCLK
Timing Path
156.25 MHz
XO
Alternate
XO
Coarse Control Voltage
26
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