QT2022/32 - Data Sheet: DS3051
5.2.6 Frame Synchronization
The frame synchronizer takes the 64 bit wide data bus output from the demultiplexer and converts it to a 66 bit wide
data bus. The 66 bits are composed of 2 sync bits followed by 64 bits of data. The sync bits are used to synchro-
nize the data stream on a frame boundary. The bus rate at each stage will depend on the selected protocol.
The chip also monitors invalid sync header bits. Valid sync bits include ‘01’ and ‘10’. The combinations ‘11’ and ‘00’
are invalid. When an invalid sync header is detected, a 6-bit counter is incremented. This counter is located in
MDIO register bits 3.33.13:8. This is a read only, non-rollover counter that is cleared when read. The counter will
count a maximum of 16 sync header errors in a 125 μs window.
When there are 16 or more sync header errors in a 125μs window, the ‘hi_ber’ flag is set to 1 in MDIO register bit
3.32.1 (3.20h.1). This is a read only register bit that is cleared when read. The algorithm for counting sync header
errors and detecting ‘hi_ber’ follows the ‘BER monitor state machine’ described in IEEE 802.3 Figure 49-13.
5.2.7 Descrambler
The descrambler processes the payload to reverse the effect of the scrambler on the payload. The descrambler is
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self-synchronizing. It calculates the inverse of the scrambler function using the polynomial 1+x +x . Only the 64
data bits are passed through the descrambler. The descrambler is bypassed when the scrambler bypass mode is
enabled through MDIO register 3.C000h.1.
Figure 4: Receive Descrambler
Scrambled Data Input
S0
S1
S2
S38
S39
S56
S57
Serial Data Output
5.2.8 66B/64B Decoder
The decoder performs the inverse function of the encoder. This block converts the 64 bit payload back into the orig-
inal eight 8-bit codes. Valid code word formats are described in IEEE 802.3-2005 Figure 49-7.
5.2.9 Receive Rate Adjust
Data from the 66B/64B decoder is written into a rate compensation FIFO using the fiber recovered clock. The out-
going data is read out using the XAUI reference clock. Due to the fact that these clocks are derived from different
sources, a rate adjust operation needs to be performed. The rate compensation block accomplishes this by either
adding or dropping Idle ordered_sets, as required, from the data stream. The minimum inter packet gap of five
characters and sequence ordered set messages are maintained.
Receive rate adjust operation is monitored in MDIO register 4.C002h. This register flags idle code removal and
insertion in bits 13:12 (normal operation), as well as overflow/underflow in bits 7:6 (fault condition).
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