QT2022/32 - Data Sheet: DS3051
If any single lane loses signal (no transitions detected), the code synchronization block will not attempt to achieve
alignment on the XAUI input lanes. The QT2022/32 will report ‘loss of sync’ on all 4 lanes.
However, when valid data is received on all 4 lanes, the code synchronization block is fully active. If no /K/ charac-
ters are detected on a given lane, the QT2022/32 will report ‘loss of sync’ independently for each lane.
5.1.3 XAUI Lane Align
The incoming XAUI data may be skewed due to varying off-chip transmission delays between the four lanes. The
deskew operation is done by aligning the /A/ code characters on all four lanes. The /A/ codes appear randomly in
the idle data stream and are transmitted simultaneously at the source on all four channels as a single column of
data, ||A||. The alignment is done by placing the data from each channel in a FIFO and adjusting the read pointer of
each FIFO so that the /A/ codes are read out simultaneously when they occur.
The QT2022/32 can tolerate a skew of up to 5 code words, or 50 bits between any two lanes at the TxXAUI input
pins. (The IEEE 802.3 requirement is for a maximum of 40 bit skew between lanes.)
5.1.4 8B/10B Decoding
Each 10 bit code word is decoded into 8 data bits and 1 control bit. The 8 data bits and 1 control bit are then
passed on to the rate adjust function.
Any 8B/10B coding errors are counted on a per lane basis. For each lane, errors are reported in an 8 bit, non-roll-
over counter that is cleared on read. The four counters for Lane 0 to Lane 3 are located in the lower byte of MDIO
registers 4.C030h - 4.C033h respectively.
5.1.5 Transmit Rate Adjust
Data is written into a rate compensation FIFO. The outgoing data is read out using a clock derived from the exter-
nal reference clock. Since these clocks are derived from different sources, a rate adjust operation needs to be
performed. The rate compensation block accomplishes this by either adding or dropping idle codes or sequence
ordered sets from the data stream. The minimum inter packet gap (IPG) of five characters and sequence ordered
set messages are always maintained.
Proper rate compensation will always be performed when the clock rates are within 200ppm (total). The QT2022/
QT2032 can tolerate up to 2 back-to-back 9600 byte jumbo frames with minimum IPG. If the clock rate difference
exceeds 200ppm or multiple back-to-back jumbo frames are transmitted, one or more packets may be corrupted.
Transmit rate adjust operation is monitored in MDIO register 4.C002h. This register flags idle code removal and
insertion in bits 15:14 (normal operation), as well as overflow/underflow in bits 9:8 (fault condition).
5.1.6 64B/66B Encoding
The encoder takes 64 bits of input data and the associated 8 bit control word and creates a new 66 bit data bus.
The 66 bits are composed of 2 sync bits followed by 64 bits of data. The sync bits are used to synchronize the data
stream on a frame boundary. The sync bits <1:0> are 10 if 64 bit data bus is composed solely of data words. If the
bus contains 1 or more control words, the sync bits <1:0> are set to 01 and are followed by a 8 bit type data. The
type word indicates the content of the following 56 bits of data. The sync bit values of 00 or 11 are invalid for the
sync bits.
Incoming control words are converted from 8 bits to 7 bits. Data words are not altered. When combinations of data
and control words are used in a bus, extra bits are inserted if needed at the boundary between the data and control
words to make the total number of bits 64. Ordered set control codes are encoded using a combination of the
block’s type field and a 4 bit O code for each ordered set.
5.1.7 Scrambler
39 58
The scrambler polynomial is 1+x +x . Only the 64 data bits pass through the scrambler. The sync bits are not
scrambled. The scrambler can be bypassed by setting the MDIO register bit 3.C000h.2.
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