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QT2032 参数 Datasheet PDF下载

QT2032图片预览
型号: QT2032
PDF下载: 下载PDF文件 查看货源
内容描述: [10 Gb/s Serial-to-XAUI PHY ICs for Ethernet and Fibre Channel LAN/ SAN/WAN Applications (CDR)]
分类和应用: 局域网
文件页数/大小: 220 页 / 2383 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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QT2022/32 - Data Sheet: DS3051  
5 Datapath Description  
This section describes the functional blocks of the QT2022/32. These are illustrated in Figure 2.  
Figure 2: QT2022/32 Functional Block Diagram  
EREFCLK  
clock  
TXPLLOUT  
SREFCLK  
(QT2032 only)  
generator  
VXCOI  
TxXAUI0  
TxXAUI1  
TxXAUI2  
TxXAUI3  
Code  
Sync  
CDR  
CDR  
CDR  
CDR  
Code  
Sync  
Phase  
Adjust &  
Demux  
Scrambler  
Output  
Driver  
64b/66b  
Encoder  
WIS  
TX  
(QT2032  
only)  
TXOUT  
Rate  
10b/8b  
Align  
Gearbox  
Mux  
Adjust  
Decoder  
Code  
Sync  
Code  
Sync  
WIS  
AMCC  
AMCC  
PMA  
3.125 Gb/s  
RxXAUI0  
XGXS  
network  
loopback  
PMA  
loopback  
XGXS  
PCS  
system  
loopback  
loopback  
network  
loopback  
system  
loopback  
(QT2032 only)  
DRV  
DRV  
DRV  
DRV  
RxXAUI1  
RxXAUI2  
RxXAUI3  
8b/10b  
Frame  
Sync  
RXIN  
WIS  
RX  
(QT2032  
De-  
scrambler  
66b/64b  
Decoder  
Rate  
Demux  
CDR  
Adjust  
Encoder  
only)  
limiting  
amp  
freq  
mon  
LOS  
detector  
RXPLLOUT  
EEPROM_SDA  
EEPROM_SCL  
MDIO  
MDC  
MDIO Control  
Interface  
EEPROM / DOM  
Interface  
sync_err  
LOSOUTB  
EEPROM_PROT  
5.1 Transmit Path  
5.1.1 XAUI CDR and Demultiplexer  
At the transmitter XAUI interface, clock and data are recovered for each of the four 3.125Gb/s input lanes. The dif-  
ferential receivers used at this interface have 100Ω differential input impedance and are intended to be AC coupled  
or 1.2V CML DC coupled. The data on each channel is then demultiplexed/deserialized before being passed to the  
next block. A clock is recovered for each lane. Each lane outputs a status bit, xtxlock<3:0>, which is high when the  
CDR circuit is in lock. A phase-adjust FIFO aligns the four lanes using the Lane 1 recovered clock.  
5.1.2 XAUI Code Synchronization  
The XAUI interface demultiplexer has no prior knowledge of code word boundaries and must determine where  
each 8B/10B character starts and ends. To achieve this, the code synchronization block searches the data stream  
for the unique comma character, /K/, in order to determine the 10 bit code word boundaries for each lane. The  
delimited code words are passed to the Frame Deskew block. The code synchronization status is displayed in Reg-  
ister bits 4.18h.3:0.  
The comma characters, /K/, are found in the XAUI data stream in the IPG between packets.  
Revision 5.11  
AppliedMicro - Confidential & Proprietary  
21  
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