Timing Model and Specifications
Table 5–28. External Timing Input Delay tGLOB Adders for GCLK Pins
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Standard
Unit
Min Max Min Max Min Max Min Max Min Max
3.3-V LVTTL Without
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
0
400
0
—
—
—
—
—
—
—
—
—
0
493
0
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
Schmitt Trigger
With Schmitt
Trigger
308
0
387
0
434
0
3.3-V
Without
LVCMOS
Schmitt Trigger
With Schmitt
Trigger
308
21
400
27
493
33
387
42
434
43
2.5-V LVTTL Without
Schmitt Trigger
With Schmitt
Trigger
423
353
855
6
550
459
1,111
7
677
565
1,368
9
429
378
681
0
476
373
622
0
1.8-V LVTTL Without
Schmitt Trigger
1.5-V LVTTL Without
Schmitt Trigger
3.3-V PCI
Without
Schmitt Trigger
Table 5–29. External Timing Output Delay and tOD Adders for Fast Slew Rate
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Standard
Unit
Min
Max Min Max
Min Max
Min
Max
Min
Max
3.3-V LVTTL
16 mA
8 mA
8 mA
4 mA
14 mA
7 mA
6 mA
3 mA
4 mA
2 mA
20 mA
—
—
—
—
—
—
—
—
—
—
—
0
65
—
—
—
—
—
—
—
—
—
—
—
0
84
—
—
—
—
—
—
—
—
—
—
—
0
104
0
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
–6
–2
3.3-V
LVCMOS
0
0
0
0
65
84
104
195
309
909
1,046
1,694
1,867
5
–6
–2
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
122
193
568
654
1,059
1,167
3
158
251
738
850
1,376
1,517
4
–63
10
–71
–1
128
352
421
757
–6
118
327
400
743
–2
5–28Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
July 2008
ALTERA [ ALTERA CORPORATION ]
