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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC and Switching Characteristics  
JTAG Timing Specifications  
Figure 5–6 shows the timing waveforms for the JTAG signals.  
Figure 5–6. MAX II JTAG Timing Waveforms  
TMS  
TDI  
t
JCP  
t
t
JPH  
JPSU  
t
t
JCL  
JCH  
TCK  
TDO  
t
t
t
JPXZ  
JPZX  
JPCO  
t
t
JSSU  
JSH  
Signal  
to be  
Captured  
t
t
t
JSXZ  
JSZX  
JSCO  
Signal  
to be  
Driven  
Table 5–34 shows the JTAG Timing parameters and values for MAX II  
devices.  
Table 5–34. MAX II JTAG Timing Parameters (Part 1 of 2)  
Symbol  
Parameter  
TCKclock period for VCCIO1 = 3.3 V  
TCKclock period for VCCIO1 = 2.5 V  
TCKclock period for VCCIO1 = 1.8 V  
TCKclock period for VCCIO1 = 1.5 V  
TCKclock high time  
Min  
55.5  
62.5  
100  
143  
20  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tJCP (1)  
tJCH  
tJCL  
TCKclock low time  
20  
tJPSU  
8
JTAG port setup time (2)  
Altera Corporation  
July 2008  
5–31  
MAX II Device Handbook, Volume 1  
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