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EPM1270GT144I4N 参数 Datasheet PDF下载

EPM1270GT144I4N图片预览
型号: EPM1270GT144I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Timing Model and Specifications  
Table 5–24. EPM570 Global Clock External I/O Timing Parameters (Part 2 of 2)  
–3 Speed  
Grade  
–4 Speed  
Grade  
–5 Speed  
Grade  
–6 Speed  
Grade  
–7 Speed  
Grade  
Cond-  
ition  
Symbol Parameter  
Unit  
Min Max Min Max Min Max Min Max Min Max  
tH  
Global  
clock hold  
time  
0.0  
0.0  
2.0  
0.0  
2.0  
0
0
ns  
tCO  
Global  
clock to  
output  
delay  
10 pF 2.0  
4.5  
5.8  
7.1  
2.0  
6.1  
2.0  
7.6  
ns  
tCH  
Global  
clock high  
time  
166  
166  
3.3  
216  
216  
4.0  
266  
266  
5.0  
253  
253  
5.4  
335  
335  
8.1  
ps  
ps  
ns  
tCL  
Global  
clock low  
time  
tCNT  
Minimum  
globalclock  
period for  
16-bit  
counter  
fCNT  
Maximum  
globalclock  
frequency  
for 16-bit  
counter  
304.0  
(1)  
247.5  
201.1  
184.1  
123.5 MHz  
Note to Table 5–24:  
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay  
performs faster than this global clock input pin maximum frequency.  
5–24Core Version a.b.c variable  
MAX II Device Handbook, Volume 1  
Altera Corporation  
July 2008  
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